Memory controllers and memory systems

Abstract

A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip includes an error correction code (ECC) engine, the ECC engine including an ECC decoder to correct Q symbols errors in a codeword set read from the memory module, Q is a maximum natural number equal to or less than P and P is a natural number equal to or greater than four. The ECC decoder is configured to generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix and to perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols.

What is claimed is: 
     
         1 . A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip, the memory controller comprising:
 an error correction code (ECC) engine, the ECC engine including an ECC decoder configured to correct Q symbol errors in a codeword set read from the memory module, Q being a maximum natural number equal to or less than P, P being a natural number equal to or greater than four;   wherein the ECC decoder is configured to:
 generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix; and 
 perform a first ECC decoding to correct a single symbol error in the read codeword set based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols; and 
   wherein the ECC decoder includes a single symbol correction circuit configured to:
 estimate an error magnitude and a position of a target symbol in which an error exists based on the first syndrome symbol and the selected syndrome symbol; 
 correct an error of the target symbol based on the estimated position of the target symbol; and 
 verify whether the error is corrected. 
   
     
     
         2 . The memory controller of  claim 1 , wherein the ECC decoder further comprises:
 a syndrome generator configured to generate the syndrome by performing a matrix-multiplication of the read codeword set with a transportation matrix of the parity check matrix.   
     
     
         3 . The memory controller of  claim 2 , wherein the single symbol correction circuit comprises:
 an error magnitude and symbol position estimator configured to estimate the first syndrome symbol as the error magnitude and configured to estimate position information of a target matrix element as the position of the target symbol, the target matrix element corresponding to a ratio of the selected syndrome symbol to the first syndrome symbol in a selected row corresponding to the selected syndrome symbol, from among a plurality of rows in the transposition matrix;   a single symbol error corrector configured to generate a corrected target symbol by adding the first syndrome symbol to an estimated target symbol corresponding to the selected syndrome symbol, from among a plurality of symbols in the read codeword set; and   an error correction checker configured to generate a check syndrome by performing a matrix-multiplication on a codeword set including the corrected target symbol and the transposition matrix and configured to determine whether the first ECC decoding is successful based on check syndrome symbols of the check syndrome.   
     
     
         4 . The memory controller of  claim 3 , wherein the error magnitude and symbol position estimator is configured to determine that the first ECC decoding fails in response to the target matrix element corresponding to the ratio of the selected syndrome symbol to the first syndrome symbol not existing in the selected row. 
     
     
         5 . The memory controller of  claim 3 , wherein the error correction checker is configured to determine that the first ECC decoding is successful in response to the check syndrome symbols being all zero. 
     
     
         6 . The memory controller of  claim 3 , wherein the error correction checker is configured to determine that the first ECC decoding fails in response to at least one of the check syndrome symbols being non-zero. 
     
     
         7 . The memory controller of  claim 2 ,
 wherein the single symbol correction circuit is configured to generate a decoding flag indicating whether the first ECC decoding is successful, and   wherein the ECC decoder further comprises:
 a multi symbol correction circuit configured to correct multi symbol errors in the read codeword set by using the first through P-th syndrome symbols and operate in parallel with the single symbol correction circuit; and 
 a control logic configured to selectively terminate an operation of the multi symbol correction circuit based on the decoding flag. 
   
     
     
         8 . The memory controller of  claim 7 , wherein the control logic is configured to terminate an operation of the multi symbol correction circuit in response to the decoding flag indicating that the first ECC decoding is successful. 
     
     
         9 . The memory controller of  claim 7 , wherein the multi symbol correction circuit comprises:
 a Berlekamp-Massey (BM) calculator configured to generate coefficients of an error locator polynomial by performing P iterations based on the first through P-th syndrome symbols;   a chien search block configured to search positions of symbol errors based on the coefficients of the error locator polynomial;   an error value estimator configured to estimate error values based on the positions of the symbol errors; and   a multi symbol error corrector configured to correct the multi symbol errors based on the estimated error values.   
     
     
         10 . The memory controller of  claim 1 , wherein the ECC decoder further comprises a multi symbol correction circuit configured to operate when the first ECC decoding fails, and
 wherein the multi symbol correction circuit is configured to perform a second ECC decoding to correct multi symbol errors in the read codeword set based on the first through P-th syndrome symbols.   
     
     
         11 . The memory controller of  claim 1 , wherein the ECC decoder further comprises:
 a syndrome generator configured to generate the syndrome by performing a matrix-multiplication on the read codeword set with a transposition matrix of the parity check matrix; and   wherein the single symbol correction circuit is further configured to:
 estimate an error magnitude and a position of a target symbol in which an error exists based on the first syndrome symbol and the selected syndrome symbol; 
 generate an estimated syndrome based on the first syndrome symbol and the estimated position of the target symbol; and 
 correct the error of the target symbol based on comparison of the estimated syndrome symbols and the syndrome symbols. 
   
     
     
         12 . The memory controller of  claim 11 , wherein the single symbol correction circuit comprises:
 an error magnitude and symbol position estimator configured to estimate the first syndrome symbol as the error magnitude and configured to search a target matrix corresponding to a ratio of the selected syndrome symbol to the first syndrome symbol in a selected row corresponding to the selected syndrome symbol, from among a plurality of rows in the transposition matrix;   an estimated syndrome generator configured to generate second through P-th estimated syndrome symbols based on a target matrix element, of the target matrix, and the first syndrome symbol;   a syndrome comparator configured to generate a comparison signal by comparing the second through P-th syndrome symbols with the second through P-th estimated syndrome symbols, respectively; and   a single symbol error corrector configured to selectively correct an error of the target symbol based on the comparison signal.   
     
     
         13 . The memory controller of  claim 12 , wherein the single symbol error corrector is, in response to each of the second through P-th syndrome symbols matching respective one of the second through P-th estimated syndrome symbols, configured to generate a corrected target symbol by adding the first syndrome symbol to the target symbol corresponding to the selected syndrome symbol, from among a plurality of symbols in the read codeword set. 
     
     
         14 . The memory controller of  claim 12 , wherein the syndrome comparator is configured to determine that the first ECC decoding fails in response to at least one pair of the second through P-th syndrome symbols and the second through P-th estimated syndrome symbols, respectively, not matching each other. 
     
     
         15 . The memory controller of  claim 11 ,
 wherein the single symbol correction circuit is configured to generate a decoding flag indicating whether the first ECC decoding is successful, and   wherein the ECC decoder further comprises:
 a multi symbol correction circuit configured to correct multi symbol errors in the read codeword set by using the first through P-th syndrome symbols and to operate in parallel with the single symbol correction circuit; and 
 a control logic configured to selectively terminate an operation of the multi symbol correction circuit based on the decoding flag. 
   
     
     
         16 . The memory controller of  claim 11 , wherein the ECC decoder further comprises a multi symbol correction circuit configured to operate when the first ECC decoding fails, and
 wherein the multi symbol correction circuit is configured to perform a second ECC decoding to correct multi symbol errors in the read codeword set based on the first through P-th syndrome symbols.   
     
     
         17 . A memory system comprising:
 a memory module that includes a plurality of data chips and at least one parity chip; and   a memory controller including a processor and configured to control the memory module,   wherein the memory controller includes:
 an error correction code (ECC) engine, the ECC engine including an ECC decoder configured to correct Q symbols errors in a codeword set read from the memory module, Q being a maximum natural number equal to or less than P, P being a natural number equal to or greater than four; 
   wherein the ECC decoder is configured to:
 generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix; 
 correct a single symbol error in the read codeword set by performing a first ECC decoding to estimate an error magnitude and a position of a target symbol in which an error exists based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols; 
 correct an error of the target symbol based on the estimated position of the target symbol; and 
 verify whether the error is corrected. 
   
     
     
         18 . The memory system of  claim 17 ,
 wherein the ECC decoder is configured to generate a decoding flag indicating whether the first ECC decoding is successful, and   wherein the ECC decoder further comprises:
 a multi symbol correction circuit configured to correct multi symbol errors in the read codeword set by using the first through P-th syndrome symbols and to operate in parallel with a single symbol correction circuit; and
 a control logic configured to selectively terminate an operation of the multi symbol correction circuit based on the decoding flag. 
 
   
     
     
         19 . The memory system of  claim 17 , wherein the memory controller is configured to control the memory module by communicating with one or hosts host through a compute express link (CXL) interface. 
     
     
         20 . A memory controller including a processor and configured to control a memory module including a plurality of data chips and at least one parity chip, the memory controller comprising:
 an error correction code (ECC) engine, the ECC engine including an ECC decoder configured to correct Q symbols errors included a codeword set read from the memory module, Q being a maximum natural number equal to or less than P, P being a natural number equal to or greater than four; and   wherein the ECC decoder is configured to:
 generate a syndrome including first through P-th syndrome symbols based on the read codeword set by using a parity check matrix; and 
 correct a single symbol error in the read codeword set by performing an ECC decoding to estimate an error magnitude and a position of a target symbol in which an error exists based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols; 
 correct an error of the target symbol based on the estimated position of the target symbol; and 
 verify whether the error is corrected.