Gates of hybrid-fin devices

Abstract

An exemplary method includes receiving a hybrid fin device layout for a hybrid fin device that includes a gate disposed over a single-fin active region and a multi-fin active region. The single-fin active region and the multi-fin active region extend lengthwise along a first direction. The gate extends lengthwise along a second direction, the second direction is different than the first direction, and the gate has a width along the first direction. The single-fin active region and a first portion of the gate form a first fin-based device having a first electrical characteristic. The multi-fin active region and a second portion of the gate form a second fin-based device having a second electrical characteristic that is different than the first electrical characteristic. The method further includes tuning the width of the gate to reduce a difference between the first electrical characteristic and the second electrical characteristic.

What is claimed is: 
     
         1 . A method comprising:
 receiving a hybrid fin device layout for a hybrid fin device, wherein the hybrid fin device layout includes:
 a single-fin active region, a multi-fin active region, and a fin partition region between the single-fin active region and the multi-fin active region, wherein the single-fin active region, the multi-fin active region, and the fin partition region extend lengthwise along a first direction, 
 a gate disposed over the single-fin active region, the multi-fin active region, and the fin partition region, wherein the gate extends lengthwise along a second direction, the second direction is different than the first direction, and the gate has a width along the first direction, and 
 the single-fin active region and a first portion of the gate form a first fin-based device having a first electrical characteristic and the multi-fin active region and a second portion of the gate form a second fin-based device having a second electrical characteristic, wherein the second electrical characteristic is different than the first electrical characteristic; 
   tuning the width of the gate to reduce a difference between the first electrical characteristic and the second electrical characteristic, wherein the tuning includes generating a modified hybrid fin device layout; and   fabricating the hybrid fin device using the modified hybrid fin device layout.   
     
     
         2 . The method of  claim 1 , wherein the tuning the width includes enlarging the width of the gate over the single-fin active region. 
     
     
         3 . The method of  claim 2 , wherein the enlarging the width of the gate over the single-fin active region includes adding a first gate extension and a second gate extension along opposites sides, respectively, of the gate over the single-fin active region. 
     
     
         4 . The method of  claim 3 , wherein the width is a first width, each of the first gate extension and the second gate extension has a second width, and the second width is about 0.15 nm to about 1.0 nm. 
     
     
         5 . The method of  claim 1 , wherein the tuning the width includes reducing the width of the gate over the single-fin active region. 
     
     
         6 . The method of  claim 1 , wherein the tuning the width includes enlarging the width of the gate over the multi-fin active region. 
     
     
         7 . The method of  claim 1 , wherein the tuning the width includes reducing the width of the gate over the multi-fin active region. 
     
     
         8 . The method of  claim 1 , wherein the first electrical characteristic is a first drain-induced barrier lowering (DIBL) and the second electrical characteristic is a second DIBL. 
     
     
         9 . The method of  claim 1 , further comprising simulating electrical performance of the hybrid fin device based on the hybrid fin device layout, wherein the tuning the width includes adjusting the width based on the simulated electrical performance. 
     
     
         10 . The method of  claim 1 , wherein the width is a first width, the tuning the width includes enlarging the first width of the gate to a second width, and the second width is about 5% to about 30% greater than the first width. 
     
     
         11 . A method comprising:
 receiving a hybrid fin device layout for a hybrid fin device, wherein the hybrid fin device includes a gate structure that is shared by a single-fin device and a multi-fin device;   based on an optical proximity correction (OPC)-based rule, determining that a difference in a first electrical characteristic of the single-fin device and a second electrical characteristic of the multi-fin device is greater than a threshold difference, wherein the first electrical characteristic and the second electrical characteristic depend on a width of the gate structure;   adjusting the width of a portion of the gate structure to reduce the difference in the first electrical characteristic and the second electrical characteristic, thereby modifying the hybrid fin device layout and improving overall electrical performance of the hybrid fin device; and   fabricating the hybrid fin device using the modified hybrid fin device layout.   
     
     
         12 . The method of  claim 11 , wherein:
 the width is a first width; and   the adjusting the width includes adding at least one jog to the portion of the gate structure, such that the portion of the gate structure has a second width that is greater than the first width.   
     
     
         13 . The method of  claim 11 , further comprising generating a simulated hybrid fin device based on the hybrid fin device layout, wherein the first electrical characteristic and the second electrical characteristic are determined from the simulated hybrid fin device. 
     
     
         14 . The method of  claim 11 , wherein:
 the width is a first width;   the portion of the gate structure is a portion of the single-fin device;   the first electrical characteristic is a first drain-induced barrier lowering (DIBL);   the second electrical characteristic is a second DIBL that is less than the first DIBL; and   the adjusting the width of the portion of the gate structure includes enlarging the portion of the gate structure from the first width to a second width to reduce a difference between the first DIBL and the second DIBL.   
     
     
         15 . A method comprising:
 receiving a hybrid fin device layout for a hybrid fin device that includes:
 a single-fin structure, a multi-fin structure, and a partition fin structure disposed between the single-fin structure and the multi-fin structure, wherein the single-fin structure, the multi-fin structure, and the partition fin structure extend lengthwise along a first direction, 
 a gate disposed over the single-fin structure, the multi-fin structure, and the partition fin structure, wherein the gate extends lengthwise along a second direction different than the first direction, 
 the single-fin structure and a first portion of the gate form a first fin-based device having a first electrical characteristic and the multi-fin structure and a second portion of the gate form a second fin-based device having a second electrical characteristic different than the first electrical characteristic, and 
 the first portion of the gate and the second portion of the gate have a first width, wherein the first width is along the first direction, and 
   increasing the first width of the first portion of the gate to a second width to reduce a difference between the first electrical characteristic and the second electrical characteristic, thereby generating a modified hybrid fin device layout; and   fabricating the hybrid fin device using the modified hybrid fin device layout.   
     
     
         16 . The method of  claim 15 , wherein a third portion of the gate is over the partition fin structure and the method further includes increasing the first width of at least a portion of the third portion of the gate to the second width. 
     
     
         17 . The method of  claim 15 , wherein:
 the single-fin structure has a first fin width along the second direction;   the multi-fin structure has a second fin width along the second direction; and   the partition fin structure has a third fin width along the second direction, wherein the third fin width is greater than the first fin width and the second fin width.   
     
     
         18 . The method of  claim 15 , wherein:
 the increasing the first width of the first portion of the gate to the second width includes adding a first gate extension and a second gate extension along opposites sides, respectively, of the first portion of the gate; and   the first gate extension has a third width along the first direction, the second gate extension has a fourth width along the first direction, the third width is less than the first width, and the fourth width is less than the first width; and   the second width is a sum of the first width, the third width, and the fourth width.   
     
     
         19 . The method of  claim 15 , wherein:
 the first electrical characteristic is a first drain-induced barrier lowering (DIBL);   the second electrical characteristic is a second DIBL different than the first DIBL; and   the first DIBL is substantially the same as the second DIBL after the increasing the first width of the first portion of the gate to the second width.   
     
     
         20 . The method of  claim 15 , wherein the first width of the first portion of the gate is increased about 0.3 nm to about 2.0 nm.