Methods and structures for three-dimensional dynamic random-access memory

Abstract

Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.

The invention claimed is: 
     
         1 . A method for forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising:
 depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material using a heteroepitaxy process onto a substrate; and   etching of a pattern of holes with at least one high aspect ratio (HAR) hole into the substrate, the pattern of holes configured to provide chemistry access to the alternating layers of c-Si material and c-SiGe material to laterally etch or deposit materials to form 3D DRAM features of the 3D DRAM structure without subsequent HAR etching of holes in the substrate to form the 3D DRAM features.   
     
     
         2 . The method of  claim 1 , further comprising:
 merging a portion of the pattern of holes formed by etching material between the portion of the pattern of holes to form an active area isolation slot of the 3D DRAM structure.   
     
     
         3 . The method of  claim 1 , further comprising:
 depositing different materials in different holes to block or allow a lateral or a vertical recess process for 3D DRAM cell formation.   
     
     
         4 . The method of  claim 1 , further comprising:
 forming an isolation slot which has a liner of a first dielectric material which is removable by exposure to hydrogen fluoride (HF) and which has ends filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and give structure support to the 3D DRAM structure.   
     
     
         5 . The method of  claim 4 , further comprising:
 forming a lower electrode of a capacitor of the 3D DRAM structure that is supported at one or more ends of the isolation slot that are filled with the second dielectric material; and   removing the liner of the first dielectric material of the isolation slot to provide space to fill with a high-k top electrode material for increased 3D DRAM cell capacitance of the 3D DRAM structure while maintaining structural support of the lower electrode.   
     
     
         6 . The method of  claim 1 , further comprising:
 etching the pattern of holes using a mask and etching process that etches both c-Si material and c-SiGe material.   
     
     
         7 . The method of  claim 1 , further comprising:
 selectively etching the c-SiGe material from inside the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole.   
     
     
         8 . The method of  claim 7 , further comprising:
 selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature; or   etching the c-Si material and the c-SiGe material in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral feature, and a width of the lateral feature that extends into the c-SiGe material.   
     
     
         9 . A method for forming a three-dimensional dynamic random-access memory (3D DRAM) structure, comprising:
 depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material using a heteroepitaxy process on a substrate;   etching of a pattern of holes with at least one high aspect ratio (HAR) hole into the substrate, the pattern of holes configured to provide chemistry access to the alternating layers of c-Si material and c-SiGe material to laterally etch or deposit materials to form 3D DRAM features of the 3D DRAM structure without subsequent HAR etching of holes in the substrate to form the 3D DRAM features;   merging a portion of the pattern of holes formed by etching material between the portion of the pattern of holes to form slot features of the 3D DRAM structure;   forming an isolation slot from at least one slot feature which has a liner of a first dielectric material which is removable by exposure to hydrogen fluoride (HF) and which has ends filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and give structure support to the 3D DRAM structure;   forming a lower electrode of a capacitor of the 3D DRAM structure that is supported at one or more ends of the isolation slot that are filled with the second dielectric material; and   removing the liner of the first dielectric material of the isolation slot to provide space to fill with a high-k top electrode material for increased 3D DRAM cell capacitance while maintaining structural support of the lower electrode.   
     
     
         10 . The method of  claim 9 , further comprising:
 etching a wordline hole between two isolation slots to form a wordline structure;   selectively etching the c-SiGe material through a top opening of the wordline hole to form lateral wordline features extending to the two isolation slots;   forming a source/drain and spacer of the 3D DRAM structure by extending the lateral wordline features until limited by the two isolation slots;   depositing a conformal layer of doped oxide in the wordline hole;   etching back the conformal layer of doped oxide to leave doped regions for a source/drain of the 3D DRAM structure;   depositing a gate oxide layer in the wordline hole; and   depositing a gate electrode to fill the wordline hole.   
     
     
         11 . The method of  claim 10 , further comprising:
 anisotropically etching a slit between two wordline structures to form a bitline structure;   selectively etching c-SiGe material laterally in the slit from a top opening of the slit;   forming the bitline structure by chemically depositing and etching from the top opening of the slit; and   forming a conductive shield layer in the bitline structure to reduce noise coupling between multiple bitlines.   
     
     
         12 . The method of  claim 9 , further comprising:
 etching the pattern of holes using a mask and etching process that etches both c-Si material and c-SiGe material.   
     
     
         13 . The method of  claim 9 , further comprising:
 selectively etching the c-SiGe material from inside the at least one HAR hole to form a lateral feature extending a sidewall of the at least one HAR hole.   
     
     
         14 . The method of  claim 13 , further comprising:
 selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature; or   etching the c-Si material and the c-SiGe material in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral feature, and a width of the lateral feature that extends into the c-SiGe material.   
     
     
         15 . The method of  claim 9 , further comprising:
 depositing different materials in different holes to block or allow a lateral or a vertical recess process for 3D DRAM cell formation.