Semiconductor memory device and method for fabricating the same

Abstract

A semiconductor memory device includes a substrate including cell and peripheral regions, a cell gate electrode disposed at the cell region, a bit line structure disposed at the cell region and including a cell conductive line and a cell line capping film disposed thereon, fin-type patterns disposed at the peripheral region, a peripheral gate electrode crossing the fin-type patterns, a peripheral gate separation pattern disposed on a sidewall of the peripheral gate electrode and having an upper surface higher than an upper surface of the peripheral gate electrode, and a peripheral interlayer insulating film covering the peripheral gate electrode, the peripheral gate separation pattern and a portion of a sidewall of the peripheral gate separation pattern. An upper surface of the peripheral interlayer insulating film and an uppermost surface of the cell line capping film are positioned at the same height relative to the substrate.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region;   a cell gate electrode disposed at the substrate of the cell region and extending in a first direction;   a bit line structure disposed at the substrate of the cell region, wherein the bit line structure includes:
 a cell conductive line extending in a second direction different from the first direction, and 
 a cell line capping film disposed on the cell conductive line; 
   a first node connection pad and a second node connection pad being spaced apart from each other in the first direction, wherein the first node connection pad and the second node connection pad are in contact with the substrate of the cell region;   a pad separation structure separating the first node connection pad and the second node connection pad from each other and covering an upper surface of the first node connection pad and an upper surface of the second node connection pad;   a plurality of fin-type patterns disposed at the substrate of the peripheral region, extending in the first direction, and being spaced apart from each other in the second direction;   a peripheral gate electrode crossing the plurality of fin-type patterns and including a first sidewall extending in the first direction and a second sidewall extending in the second direction;   a peripheral gate separation pattern disposed on the first sidewall of the peripheral gate electrode and having an upper surface higher than an upper surface of the peripheral gate electrode; and   a peripheral interlayer insulating film covering the upper surface of the peripheral gate electrode, the upper surface of the peripheral gate separation pattern and a portion of a sidewall of the peripheral gate separation pattern,   wherein an upper surface of the peripheral interlayer insulating film and an uppermost surface of the cell line capping film are positioned at the same height relative to the substrate, and   wherein the cell conductive line is disposed on an upper surface of the pad separation structure.   
     
     
         2 . The semiconductor memory device of  claim 1 , further comprising:
 a fin trench separating the plurality of fin-type patterns adjacent to each other in the second direction from each other; and   a cell gate trench disposed in the substrate of the cell region,   wherein the cell gate electrode is disposed in the cell gate trench, and   wherein a depth of the cell gate trench is the same as a depth of the fin trench.   
     
     
         3 . The semiconductor memory device of  claim 2 ,
 wherein the cell gate trench is disposed at the cell active region, and   wherein a depth of the cell gate trench in the cell active region is the same as the depth of the fin trench.   
     
     
         4 . The semiconductor memory device of  claim 1 ,
 wherein the plurality of fin-type patterns include a first fin-type pattern including a first sidewall and a second sidewall opposite to each other in the second direction, and   wherein a height of the first sidewall of the first fin-type pattern is different from a height of the second sidewall of the first fin-type pattern.   
     
     
         5 . The semiconductor memory device of  claim 1 , further comprising:
 a peripheral gate insulating film disposed between the peripheral gate electrode and each of the plurality of fin-type patterns,   wherein the peripheral gate insulating film extends along the sidewall of the peripheral gate separation pattern.   
     
     
         6 . The semiconductor memory device of  claim 1 , further comprising:
 a pair of source/drain regions disposed on opposite sidewalls of the peripheral gate electrode,   wherein the pair of source/drain regions include a semiconductor epitaxial pattern disposed at a corresponding fin-type pattern of the plurality of fin-type patterns.   
     
     
         7 . The semiconductor memory device of  claim 1 , further comprising:
 a bit line contact connecting the cell conductive line to the cell active region,   wherein the bit line contact includes a portion with a decreasing width toward the cell active region.   
     
     
         8 . The semiconductor memory device of  claim 1 , further comprising:
 an information storage part disposed on the cell region; and   a storage pad connecting the first node connection pad to a lower electrode of the information storage part,   wherein the storage pad contacts the uppermost surface of the cell line capping film.   
     
     
         9 . A semiconductor memory device comprising:
 a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region;   a cell element separation film on the substrate and defining the cell active region;   a cell gate structure disposed at the substrate of the cell region, wherein the cell gate structure includes:
 a cell gate trench extending in a first direction across the cell element separation film and the cell active region, wherein the cell gate trench extends from an upper surface of the cell element separation film toward a bottom surface of the substrate, and 
 a cell gate electrode in the cell gate trench; 
   a bit line structure disposed at the substrate of the cell region, wherein the bit line structure includes:
 a cell conductive line extending in a second direction different from the first direction, and 
 a cell line capping film disposed on the cell conductive line; 
   a plurality of fin-type patterns disposed at the substrate of the peripheral region, extending in the first direction, and being spaced apart from each other in the second direction;   a fin trench separating the plurality of fin-type patterns adjacent to each other in the second direction from each other, wherein the fin trench extends from an upper surface of a first fin-type pattern of the plurality of fin-type patterns adjacent to the fin trench toward the bottom surface of the substrate;   a peripheral gate electrode crossing the plurality of fin-type patterns; and   a peripheral interlayer insulating film disposed on the peripheral gate electrode,   wherein a depth of the cell gate trench relative to the upper surface of the cell element separation film is the same as a depth of the fin trench relative to the upper surface of the first fin-type pattern of the plurality of fin-type patterns adjacent to the fin trench.   
     
     
         10 . The semiconductor memory device of  claim 9 ,
 wherein the depth of the cell gate trench and the depth of the fin trench are measured from the upper surface of the cell element separation film.   
     
     
         11 . The semiconductor memory device of  claim 9 , further comprising:
 a peripheral gate spacer disposed on a sidewall of the peripheral gate electrode,   wherein an upper surface of the peripheral gate electrode is lower than an upper surface of the peripheral gate spacer.   
     
     
         12 . The semiconductor memory device of  claim 11 , further comprising:
 a peripheral gate insulating film disposed between the peripheral gate electrode and a corresponding fin-type pattern of the plurality of fin-type patterns,   wherein the peripheral gate insulating film extends along a sidewall of the peripheral gate spacer.   
     
     
         13 . The semiconductor memory device of  claim 9 , further comprising:
 a pair of source/drain regions disposed on opposite sidewalls of the peripheral gate electrode,   wherein the pair of source/drain regions include a semiconductor epitaxial pattern connected to a corresponding fin-type pattern of the plurality of fin-type patterns.   
     
     
         14 . The semiconductor memory device of  claim 9 , further comprising:
 a first node connection pad and a second node connection pad being spaced apart from each other in the first direction, wherein the first node connection pad and the second node connection pad are in contact with the substrate of the cell region; and   a pad separation structure separating the first node connection pad and the second node connection pad from each other and covering an upper surface of the first node connection pad and an upper surface of the second node connection pad.   
     
     
         15 . The semiconductor memory device of  claim 14 ,
 wherein the pad separation structure includes a pad separation pattern and a cell insulating film disposed on the pad separation pattern,   wherein the pad separation pattern separates the first node connection pad and the second node connection pad from each other, and   wherein the cell insulating film covers the upper surface of the first node connection pad and the upper surface of the second node connection pad.   
     
     
         16 . A semiconductor memory device comprising:
 a substrate including a cell region and a peripheral region surrounding the cell region, the cell region including a cell active region;   a plurality of cell gate electrodes disposed at the substrate of the cell region and extending in a first direction;   a bit line structure disposed at the substrate of the cell region, wherein the bit line structure includes:
 a cell conductive line extending in a second direction different from the first direction, and 
 a cell line capping film disposed on the cell conductive line; 
   a plurality of fin-type patterns disposed at the substrate of the peripheral region, extending in the first direction, and being spaced apart from each other in the second direction;   a plurality of fin trenches separating the plurality of fin-type patterns from each other and being spaced apart from each other in the second direction;   a peripheral gate electrode crossing the plurality of fin-type patterns; and   a peripheral interlayer insulating film disposed on the peripheral gate electrode,   wherein an interval between two adjacent cell gate electrodes of the plurality of cell gate electrodes spaced apart from each other in the second direction is the same as an interval between two adjacent fin trenches of the plurality of fin trenches spaced apart from each other in the second direction.   
     
     
         17 . The semiconductor memory device of  claim 16 , further comprising:
 a peripheral gate spacer disposed on a sidewall of the peripheral gate electrode; and   a peripheral gate insulating film disposed between the peripheral gate electrode and a corresponding fin-type pattern of the plurality of fin-type patterns,   wherein the peripheral gate insulating film extends along a sidewall of the peripheral gate spacer.   
     
     
         18 . The semiconductor memory device of  claim 16 , further comprising:
 a cell gate trench disposed in the substrate of the cell region,   wherein the cell gate trench is filled with a corresponding cell gate electrode of the plurality of cell gate electrodes, and   wherein a depth of the cell gate trench is the same as depths of the plurality of fin trenches.