Protocol including timing calibration between memory request and data transfer

Abstract

The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request.

What is claimed is: 
     
         1 . An integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the IC memory controller comprising:
 a command interface to transmit, to the IC memory device, a read command and a phase adjustment command, wherein the phase adjustment command specifies a phase adjustment operation, to be performed by the IC memory device, in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to receiving the read command, wherein the IC memory device suspends the internal clock circuitry after outputting the data;   a data interface to receive the data; and   a transmitter to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.   
     
     
         2 . The IC memory controller according to  claim 1 , embodied as a volatile IC memory controller to control at least one volatile IC memory device. 
     
     
         3 . The IC memory controller according to  claim 1 , further comprising:
 a locked loop circuit to generate the timing reference signal.   
     
     
         4 . The IC memory controller according to  claim 3 , wherein the command interface is to transmit the phase adjustment command after the read command, and wherein the read command and the phase adjustment command are separated by a time for the IC memory device to lock the locked loop circuit. 
     
     
         5 . The IC memory controller according to  claim 1 , wherein:
 the IC memory device suspends the internal clock circuitry by disabling a power source that supplies power to the internal clocking circuitry.   
     
     
         6 . The IC memory controller according to  claim 5 , wherein:
 the command interface is to transmit a sleep command to the IC memory device, wherein the sleep command specifies disabling the power source that supplies power to the internal clocking circuitry.   
     
     
         7 . The IC memory controller according to  claim 1 , wherein:
 the phase adjustment operation involves the IC memory device calibrating a phase of the timing reference signal to be used in outputting the data by the IC memory device.   
     
     
         8 . A method of operation in an integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the method comprising:
 transmitting, via a command interface, a read command and a phase adjustment command to an IC memory device, wherein the phase adjustment command specifies a phase adjustment operation to be performed by the IC memory device in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to the read command;   receiving the data via a data interface; and   transmitting a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.   
     
     
         9 . The method of  claim 8 , wherein the transmitting, via the command interface, of the read command and the phase adjustment command to the IC memory device comprises:
 transmitting the read command and the phase adjustment command in accordance with a volatile memory protocol.   
     
     
         10 . The method of  claim 8 , further comprising transmitting a second command to the IC memory device after the phase adjustment operation, the second command to signal the outputting of the data in connection with the read command. 
     
     
         11 . The method of  claim 8 , further comprising:
 after the IC memory device outputs the data, suspending the internal clock circuitry.   
     
     
         12 . The method of  claim 11 , wherein the IC memory device employs a power source for the internal clocking circuitry that is associated with the memory interface of the IC memory device. 
     
     
         13 . The method of  claim 12 , wherein the phase adjustment command is transmitted after the read command, the method further comprising:
 transmitting, via the command interface, a sleep command to the IC memory device, after the data interface receives the data, wherein the sleep command specifies disabling the power source associated with the memory interface of the IC memory device.   
     
     
         14 . The method according to  claim 8 , wherein:
 the phase adjustment operation involves the IC memory device calibrating a phase of the timing reference signal.   
     
     
         15 . An integrated circuit (IC) memory controller to control operation of an IC memory device comprising a memory array and a memory interface that comprises internal clocking circuitry, the IC memory controller comprising:
 command interface circuitry to transmit command information to the IC memory device, wherein in response to receiving at least a portion of the command information, the IC memory device enables clock signal propagation from the internal clocking circuitry, wherein the command information specifies:
 (i) a read operation in which data is accessed from the memory array, and 
 (ii) a phase adjustment operation to be performed by the IC memory device in an intervening time between receiving the command information and outputting the data accessed from the memory array; and 
   data interface circuitry to receive the data;   transmit circuitry to transmit a timing reference signal to the IC memory device, the timing reference signal to time outputting of the data by the IC memory device.   
     
     
         16 . The IC memory controller according to  claim 15 , embodied as a volatile IC memory controller to control at least one volatile IC memory device. 
     
     
         17 . The IC memory controller according to  claim 15 , wherein the command interface circuitry is to transmit a second command after the phase adjustment operation, the second command to signal the outputting of the data in connection with the read operation. 
     
     
         18 . The IC memory controller according to  claim 15 , wherein:
 after outputting the data, the IC memory device suspends the internal clocking circuitry.   
     
     
         19 . The IC memory controller according to  claim 18 , wherein:
 the command interface circuitry is to transmit a sleep command to the IC memory device, wherein the sleep command specifies disabling a power source that supplies power to the internal clocking circuitry.   
     
     
         20 . The IC memory controller according to  claim 15 , wherein:
 the phase adjustment operation involves the IC memory device calibrating a phase of the timing reference signal to be used in outputting the data by the IC memory device.