Method of generating in-phase and quadrature-phase clock signals

Abstract

A clock signal generator, including: an in-phase clock generating circuit, comprising: an inverter configured to invert an input clock signal to generate a substantially square wave voltage; and a first transimpedance amplifier (TIA) configured to generate an in-phase clock signal based on the substantially square wave voltage; and a quadrature-phase clock generating circuit comprising: a load capacitor; a switched integrator configured to integrate the input clock signal to generate a substantially triangular wave voltage across the load capacitor; and a second transimpedance amplifier (TIA) configured to generate a quadrature-phase clock signal based on the substantially triangular wave voltage.

What is claimed: 
     
         1 . A clock signal generator, comprising:
 an in-phase clock generating circuit, comprising:
 an inverter configured to invert an input clock signal to generate a substantially square wave voltage; and 
 a first transimpedance amplifier (TIA) configured to generate an in-phase clock signal based on the substantially square wave voltage; and 
   a quadrature-phase clock generating circuit comprising:
 a load capacitor; 
 a switched integrator configured to integrate the input clock signal to generate a substantially triangular wave voltage across the load capacitor; and 
 a second transimpedance amplifier (TIA) configured to generate a quadrature-phase clock signal based on the substantially triangular wave voltage. 
   
     
     
         2 . The clock signal generator of  claim 1 , wherein the switched integrator comprises:
 a p-channel field effect transistor (PFET);   a first current source;   a second current source; and   an n-channel field effect transistor (NFET), wherein the PFET, the first current source, the second current source, and the NFET are coupled in series between an upper voltage rail and a lower voltage rail, wherein an output of the switched integrator is between the first current source and the second current source.   
     
     
         3 . The clock signal generator of  claim 2 , wherein the load capacitor is coupled between the output of the switched integrator and the lower voltage rail. 
     
     
         4 . The clock signal generator of  claim 2 , further comprising a common mode control circuit including an input coupled to the output of the switched integrator and at least one output coupled to one or both of the first current source or the second current source. 
     
     
         5 . The clock signal generator of  claim 1 , further comprising a calibration capacitor coupled between an output of the inverter and a lower voltage rail. 
     
     
         6 . The clock signal generator of  claim 1 , wherein the first TIA comprises:
 an inverting amplifier;   an alternating current (AC) capacitor coupled between an output of the inverter and an input of the inverting amplifier; and   a feedback resistor coupled between an output and the input of the inverting amplifier.   
     
     
         7 . The clock signal generator of  claim 1 , wherein the in-phase clock generating circuit further comprises one or more cascaded inverters or buffers including an input coupled to an output of the first TIA, wherein the one or more cascaded inverters or buffers are configured to generate the in-phase clock signal. 
     
     
         8 . The clock signal generator of  claim 1 , wherein the second TIA comprises:
 an inverting amplifier;   an alternating current (AC) capacitor coupled between an output of the switched integrator and an input of the inverting amplifier; and   a feedback resistor coupled between an output and the input of the inverting amplifier.   
     
     
         9 . The clock signal generator of  claim 1 , wherein the quadrature-phase clock generating circuit further comprises one or more cascaded inverters or buffers including an input coupled to an output of the second TIA, wherein the one or more cascaded inverters or buffers are configured to generate the quadrature-phase clock signal. 
     
     
         10 . A method of generating quadrature clock signals, comprising:
 inverting an input clock signal to generate an in-phase clock signal;   integrating the input clock signal to generate a triangular wave voltage; and   converting the triangular wave voltage into a square wave to generate a quadrature-phase clock signal.   
     
     
         11 . The method of  claim 10 , wherein integrating the input clock signal comprises:
 supplying a charging current to a load capacitor to generate an increasing portion of the triangular wave voltage in response to a low logic state of the input clock signal; and   drawing a discharging current from the load capacitor to generate a decreasing portion of the triangular wave voltage in response to a high logic state of the input clock signal.   
     
     
         12 . The method of  claim 11 , further comprising calibrating the charging current and the discharging current based on a frequency of the input clock signal. 
     
     
         13 . The method of  claim 12 , wherein calibrating the charging current and the discharging current based on the frequency of the input clock signal comprises increasing or decreasing the charging current and the discharging current in response to increasing or decreasing the frequency of the input clock signal, respectively. 
     
     
         14 . The method of  claim 11 , further comprising calibrating a capacitance of the load capacitor based on a frequency of the input clock signal. 
     
     
         15 . The method of  claim 14 , wherein calibrating the capacitance of the load capacitor based on the frequency of the input clock signal comprises increasing or decreasing the capacitance of the load capacitor in response to decreasing or increasing the frequency of the input clock signal, respectively. 
     
     
         16 . The method of  claim 10 , further comprising tuning a calibration capacitor to adjust a phase of the in-phase clock signal so that a phase difference between the in-phase clock signal and the quadrature-phase clock signal is substantially 90 degrees. 
     
     
         17 . The method of  claim 10 , wherein converting the triangular wave voltage into a square wave to generate the quadrature-phase clock signal comprises comparing the triangular wave voltage to a threshold. 
     
     
         18 . The method of  claim 10 , wherein converting the triangular wave voltage into a square wave to generate the quadrature-phase clock signal comprises amplifying the triangular wave voltage with a transimpedance gain. 
     
     
         19 . The method of  claim 10 , wherein inverting an input clock signal to generate an in-phase clock signal, comprises:
 generating a square wave voltage by inverting the input clock signal; and   amplifying the square wave voltage with a transimpedance gain.   
     
     
         20 . The method of  claim 10 , further comprising:
 buffering the in-phase clock signal; and   buffering the quadrature-phase clock signal.