VPX bank architecture

Abstract

A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.

What is claimed is:  
     
         1 . A method of arranging a memory array comprising: 
 segmenting said memory array into at least two banks, said banks comprising of memory cells; and    providing said banks with a supply voltage.    
     
     
         2 . The method of    claim 1    wherein each of said banks comprises a set of X-decoder cells.  
     
     
         3 . The method of    claim 1    wherein each of said sets of X-decoder cells has a separate N-well.  
     
     
         4 . The method of    claim 1    wherein said providing comprises coupling said supply voltage from a global signal to a local signal.  
     
     
         5 . The method of    claim 1    wherein said each of said banks comprises bank switch logic, said switch logic coupling a global signal to a local signal.  
     
     
         6 . A method for reducing program current comprising: 
 segmenting a capacitance that has to be charged; and    inserting a dummy row in a memory array.    
     
     
         7 . The method of    claim 6    wherein said dummy row is an unused wordline to keep said memory array contiguous.  
     
     
         8 . The method of    claim 6    wherein said two dummy rows are inserted into said memory array.  
     
     
         9 . The method of    claim 6    wherein said segmenting comprises dividing a memory array into a plurality of banks, each of said banks comprising memory cells.  
     
     
         10 . The method of    claim 9    wherein each of said banks comprises a set of X-decoder cells.  
     
     
         11 . The method of    claim 9    wherein N-wells of said banks are separate.  
     
     
         12 . The method of    claim 9    further comprising generating local signals for each of said banks.  
     
     
         13 . The method of    claim 12    wherein said generating comprises using switching logic to couple global signals to said local signals.  
     
     
         14 . The method of    claim 9    wherein each of said banks comprises of switching logic.  
     
     
         15 . The method of    claim 9    wherein a bank is activated when an address in said bank is accessed.  
     
     
         16 . An apparatus for accessing memory comprising: 
 a global signal;    a memory array coupled to said global signal, said memory array segmented into at least two banks, said banks comprising memory cells.    
     
     
         17 . The apparatus of    claim 16    further comprising a charge pump, said charge pump providing a pumped supply voltage.  
     
     
         18 . The apparatus of    claim 17    wherein said charge pump is coupled to high voltage switch logic, said high voltage logic for switching said pumped supply voltage to a global signal.  
     
     
         19 . The apparatus of    claim 16    wherein each of said banks comprises bank switching logic, said bank switching logic for coupling said global signal to a local signal within in each of said banks.  
     
     
         20 . The apparatus of    claim 16    wherein each of said banks comprises a set of X-decoder cells, each set of X-decoder cells coupled to bank switching logic.  
     
     
         21 . The apparatus of    claim 20    wherein each of said X-decoder cells couples said local signal to a global wordline.  
     
     
         22 . The apparatus of    claim 16    wherein N-wells of said banks are separate.  
     
     
         23 . The apparatus of    claim 16    wherein said memory array further comprises a dummy row, said dummy row located between said banks.  
     
     
         24 . The apparatus of    claim 23    wherein said dummy row is an unused wordline to keep said memory array contiguous.  
     
     
         25 . The apparatus of    claim 21    wherein a local block select device is coupled to said global wordline, said local block select device to connect said global wordline to a local wordline depending on address of memory address being accessed.  
     
     
         26 . A memory comprising: 
 a charge pump, said charge pump to provide a pumped supply voltage;    an X-path switch coupled to said charge pump, said X-path switch for coupling said pumped supply voltage to a global signal; and    a memory array, said memory array segmented into at least two banks, each bank comprising 
 bank switch logic for coupling said global signal to a local signal;  
 a set of X-decoders coupled to said local signal, said X-decoders coupled to global wordlines; and  
 local block selects to connect said global wordlines to local wordlines.  
   
     
     
         27 . The memory of    claim 26    wherein N-wells of each set of X-decoders are separate.  
     
     
         28 . The memory of    claim 26    wherein said memory array further comprises a dummy row, said dummy row located between said banks to keep said memory array contiguous.  
     
     
         29 . The memory of    claim 26    wherein said memory is a flash memory.  
     
     
         30 . A digital processing system comprising: 
 a processor;    a memory coupled to said processor, said memory comprising a memory array, said memory array segmented into at least two banks, each bank comprising 
 bank switch logic for coupling a global signal to a local signal;  
 a set of X-decoders coupled to said local signal, said X-decoders coupled to global wordlines; and  
 local block selects to connect said global wordlines to local wordlines.