Copper metallization structure and method of construction

Abstract

The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO 2 ), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface. The resulting product is then exposed to an electrochemical deposition or electroplating stage for the formation of a copper layer directly on top of the diffusion barrier layer. In accordance with a preferred embodiment of the invention, a variable voltage is applied to the electrochemical process in two different stages. The first stage produces nucleation of a high density of clusters and the second stage permits diffusion limited growth of the clusters so as to produce a continuous copper film layer.

What is claimed as new and desired to be protected by Letters Patent of the United States is:  
     
         1 . A process of fabricating a conductive layer on a substrate, the process comprising the steps of: 
 preparing a boundary layer on the substrate; and    depositing a conductive layer on the boundary layer, wherein said depositing step comprises the substeps of applying a first control parameter until a condition subsequent occurs, and applying a second control parameter after occurrence of the condition subsequent.    
     
     
         2 . The process of fabricating a conductive layer of    claim 1   , wherein the semiconductor substrate is silicon, the conductive layer is a metallic material having diffusion limited by the boundary layer, wherein the boundary layer is a diffusion barrier layer, and wherein said substep of applying a first control parameter includes applying a first voltage, and said substep of applying a second control parameter includes applying a second voltage which is more positive than the first voltage.  
     
     
         3 . The process of fabricating a conductive layer of    claim 2   , wherein the diffusion barrier layer is a transition metal-based material, and the conductive layer is copper.  
     
     
         4 . The process of fabricating a conductive layer of    claim 3   , wherein the diffusion barrier layer is titanium nitride, and said depositing step includes passing the semiconductor substrate through an aqueous solution of copper ions.  
     
     
         5 . The process of fabricating a conductive layer of    claim 1   , wherein said substep of applying a first control parameter involves application of a negative voltage sufficient to produce nucleation of a high density of hemispherical clusters to make up the conductive layer, and wherein said substep of applying a second control parameter involves increasing the applied first control parameter to a level that permits growth of the hemispherical clusters to form a continuous and adherent film.  
     
     
         6 . The process of fabricating a conductive layer of    claim 5   , wherein the negative voltage is between −0.4 V and −1.0 V.  
     
     
         7 . The process of fabricating a conductive layer of    claim 6   , wherein the negative voltage is increased during said substep of applying a second control parameter to a level between −0.10 V and 0.05 V.  
     
     
         8 . The process of fabricating a conductive layer of    claim 5   , wherein the condition subsequent is a predetermined level of density of the hemispherical clusters formed as a result of the substep of applying a first voltage.  
     
     
         9 . The process of fabricating a conductive layer of    claim 1   , wherein the first control parameter is a first current level, and the second control parameter is a second current level which is smaller than the first current level.  
     
     
         10 . A process of depositing copper on a semiconductor substrate, the process comprising the steps of: 
 forming a dielectric layer on at least one surface of the semiconductor substrate;    depositing a boundary layer on the dielectric layer such that said boundary layer is capable of preventing substantial diffusion of copper; and    depositing copper material on the boundary layer by utilizing an electrochemical deposition bath of copper ions through first and second applied voltage potentials such that a layer of copper is produced.    
     
     
         11 . The process of depositing copper as recited in    claim 10   , wherein said step of forming a dielectric layer comprises the step of forming a layer of silicon dioxide using chemical vapor deposition.  
     
     
         12 . The process of depositing copper as recited in    claim 10   , wherein said step of depositing a boundary layer comprises the step of depositing a layer of material containing titanium through RF sputtering for one minute at an RF voltage of approximately 650 Volts.  
     
     
         13 . The process of depositing copper as recited in    claim 10   , wherein said step of depositing copper material involves placing the semiconductor substrate through an aqueous solution of copper ions.  
     
     
         14 . The process of depositing copper as recited in    claim 10   , wherein said step of depositing copper material is an electrochemical deposition process that uses a bath having a solution with a pH in a range from 1.0 to 2.0.  
     
     
         15 . The process of depositing copper as recited in    claim 10   , further comprising the step of providing an ohmic contact to said silicon wafer.  
     
     
         16 . The process of depositing copper as recited in    claim 10   , wherein said step of depositing copper material on the boundary layer involves application of a first voltage in the range −0.7 V and −1 V, followed by application of a second voltage in the range −0.10 V and 0.05 V.  
     
     
         17 . A semiconductor chip fabricated by a method of metallizing an integrated circuit using copper to form via and interconnect structures, the method comprising: 
 step for forming first dielectric layer on at least one planar surface of a silicon wafer containing a plurality of semiconductor electronic devices;    step for depositing a diffusion layer on said dielectric layer such that said diffusion layer prevents diffusion of copper;    step for forming a masking layer such that via and interconnect locations are defined for the semiconductor electronic devices;    step for depositing a layer of copper film over the masking layer and the diffusion layer, wherein said step of depositing a layer of copper film comprises: 
 step for submersing the silicon wafer in an electrolytic bath containing copper ions;  
 step for applying a first voltage pulse to the electrolytic bath to form copper clusters on the masking layer and the diffusion layer; and  
 step for applying a second voltage at a level more positive than the first voltage pulse to grow the copper clusters to obtain a continuous copper film layer;  
   step for selectively removing the continuous copper film layer to form patterned copper via and interconnect structures.    
     
     
         18 . The process of metallizing an integrated circuit as recited in    claim 17   , wherein the silicon wafer is made of n-type silicon, the dielectric layer is made of silicon dioxide, and the diffusion layer is made of titanium nitride.  
     
     
         19 . The process of metallizing an integrated circuit as recited in    claim 18   , wherein the dielectric layer is formed by spin coating, and wherein the diffusion layer is deposited by physical vapor deposition to a thickness of 20-40 nanometers.  
     
     
         20 . The process of metallizing an integrated circuit as recited in    claim 19   , wherein the electrolytic bath is prepared from CuCO3 Cu(OH) 2  with H 3 B0 3  and HBF 4  and surfynol with a pH between 1.0 and 2.0 CUCO 3 .