Method of manufacturing a semiconductor integrated circuit device

Abstract

Oxidation on the surface of a film of refractory metal constituting a gate electrode (word line WL) is suppressed by forming an insulation film constituting a cap insulation film of the gate electrode (word line WL) at a temperature of 500° C. or lower. Further, oxidation on the surface of the refractory metal film exposed to the side wall of the gate electrode (word line WL) is suppressed by forming an insulation film constituting the side wall spacer of the gate electrode (word line WL) at a temperature of 500° C. or lower.

What is claimed is:  
     
         1 . A method of manufacturing a semiconductor integrated circuit device having a MISFET, comprising: 
 (a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,    (b) a step of forming a gate electrode by etching the first insulation film and the gate electrode material using a photoresist as a mask,    (c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,    (d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film, and    (e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film using a photoresist as a mask, to form a contact hole for the connection of wiring to one of the source region and the drain region.    
     
     
         2 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 1   , wherein the first and the second insulation films are silicon nitride films and the third insulation film is a silicon oxide film.  
     
     
         3 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 2   , wherein the silicon nitride film is deposited by a plasma CVD method.  
     
     
         4 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 1   , wherein the first and the second insulation films are silicon oxide films and the third insulation film is a silicon nitride film.  
     
     
         5 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 4   , wherein the silicon oxide film is deposited by a plasma CVD method.  
     
     
         6 . A method of manufacturing a semiconductor integrated circuit device having MISFET, comprising: 
 (a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,    (b) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the first insulation film at a temperature of 500° C. or higher and then etching the second insulation film, the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode,    (c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region,    (d) a step of depositing a third insulation film having an etching rate approximately identical with that of the first and the second insulation films over the gate electrode at a temperature of 500° C. or lower, depositing a fourth insulation film having an etching rate approximately identical with that of the third insulation film at a temperature of 500° C. or higher over the third insulation film and then etching the fourth and the third insulation films, to form a side wall spacer on the side wall of the gate electrode and the first and the second insulation films, and    (e) a step of depositing a fifth insulation film having an etching rate different from those of the first to fourth insulation films over the gate electrode and then etching the fifth insulation film by using a photoresist as a mask, to form a contact hole for connection of wiring to one of the source region and the drain region.    
     
     
         7 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 6   , wherein the first to fourth insulation films are silicon nitride films and the fifth insulation film is a silicon oxide film.  
     
     
         8 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 6   , wherein the first to fourth insulation films are silicon oxide films and the fifth insulation film is a silicon nitride film.  
     
     
         9 . A method of manufacturing a semiconductor integrate circuit device having a DRAM provided with a memory cell of a stacked capacitor structure in which bit lines are disposed over a memory selection MISFET and information storage capacitors are disposed over the bit lines, comprising: 
 (a) a step of depositing a gate electrode material containing a refractory metal film over a semiconductor substrate and depositing a first insulation film over the gate electrode material at a temperature of 500° C. or lower,    (b) a step of etching the first insulation film and the gate electrode material using a photoresist as a mask, to form a gate electrode for a memory cell selection MISFET,    (c) a step of introducing impurities into the semiconductor substrate, to form a source region and a drain region of a memory cell selection MISFET,    (d) a step of depositing a second insulation film having an etching rate approximately identical with that of the first insulation film over the gate electrode at a temperature of 500° C. or lower and then etching the second insulation film, to form a side wall spacer to the side wall of the gate electrode and the first insulation film,    (e) a step of depositing a third insulation film having an etching rate different from those of the first and the second insulation films over the gate electrode and then etching the third insulation film by using a photoresist as a mask, to form a first contact hole for the connection of a bit line to one of the source region and the drain region, and a second contact hole for connection of a lower electrode of the information storage capacitor to the other of the source region and the drain region,    (f) a step of burying plugs to the inside of the first and the second contact holes, depositing a bit line material containing at least one layer of a metal film over the third insulation film and then depositing a fourth insulation film over the bit line material at a temperature of 500° C. or lower,    (g) a step of etching the fourth insulation film and the bit line material by using a photoresist as a mask to form a bit line,    (h) a step of depositing a fifth insulation film having an etching rate approximately identical with that of the fourth insulation film over the bit line at a temperature of 500° C. or lower and then etching the fifth insulation film, to form a side wall spacer to the side wall of the bit line and the fourth insulation film, and    (i) a step of depositing a sixth insulation film having an etching rate different from those of the fourth and fifth insulation films over the bit line and then etching the sixth insulation film by using a photoresist as a mask, to form a third contact hole over the second contact hole for connecting the lower electrode of the information storage capacitor and the other of the source region and the drain region.    
     
     
         10 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 9   , wherein the first, second, fourth and fifth insulation films are silicon nitride films and the third and sixth insulation films are silicon oxide films.  
     
     
         11 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 9   , wherein the first, second, fourth and fifth insulation films are silicon oxide film and the third and sixth insulation films are silicon nitride films.  
     
     
         12 . A method of manufacturing a semiconductor integrated circuit device as defined in any one of    claims 1    to    11   , wherein metal film is a tungsten film.  
     
     
         13 . A method of manufacturing a semiconductor integrated circuit device having a MISFET with source, drain and gate, comprising: 
 (a) a step of depositing a first conductive film of a refractory metal over a main surface of a semiconductor substrate and a first silicon nitride film by a plasma CVD method on the first conductive film,    (b) a step of fabricating the first conductive film and the silicon nitride film into a predetermined pattern, to form a gate electrode of the MISFET,    (c) a step of introducing impurities into the semiconductor substrate in an self alignment manner to the gate electrode for forming semiconductor regions that function as the source and the drain,    (d) a step of depositing a second silicon nitride film over the gate electrode by a plasma CVD method,    (e) a step of applying anisotropic etching to the second silicon nitride film, to form a side wall spacer on the side of the gate electrode,    (f) a step of depositing an oxide film over the gate electrode and the side wall spacer, and    (g) a step of applying etching to the oxide film for forming an opening to expose a portion of the semiconductor region.    
     
     
         14 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 13   , wherein the first conductive film is formed from a refractory metal by a sputtering method.  
     
     
         15 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 14   , further including a step of depositing a polysilicon film and a film for preventing reaction between the polysilicon film and the conductive film over the semiconductor substrate before forming the first conductive film.  
     
     
         16 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 15   , further including a step of forming a titanium nitride film as the reaction preventive film.  
     
     
         17 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 13   , further including a step of applying chemical and mechanical polishing to the surface of the oxide film after depositing the oxide film.  
     
     
         18 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 17   , further including a step of forming a second conductive film in the aperture.  
     
     
         19 . A method of manufacturing a semiconductor integrated circuit device having a MISFET with source, drain and gate, comprising: 
 (a) a step of depositing a first conductive film comprising a refractory metal over a main surface of a semiconductor substrate and a first insulation film on the first conductive film by a plasma CVD method,    (b) a step of fabricating the first conductive film and the first insulation film into a predetermined pattern, to form a gate electrode of the MISFET,    (c) a step of introducing impurities into the semiconductor substrate in a self-alignment manner to the gate electrode for forming semiconductor regions that function as the source and the drain,    (d) a step of depositing a second insulation film over the gate electrode by a plasma CVD method,    (e) a step of applying anisotropic etching to the second insulation film, to form a side wall spacer on the side wall of the gate electrode,    (f) a step of depositing a third insulation film over the gate electrode and the side wall spacer, and    (g) a step of applying etching to the third insulation film for forming an opening to the third insulation film for exposing a portion of the semiconductor region,    wherein the etching rate of the first and the second insulation films is lower than the etching rate of the third insulation film in the etching step for forming the opening.    
     
     
         20 . A method of manufacturing a semiconductor integrated circuit device having a MISFET with source, drain and gate, comprising: 
 (a) a step of depositing a first conductive film of a refractory metal over a main surface of a semiconductor substrate, a first silicon nitride film on the first conductive film and a second silicon nitride film on the first silicon nitride film,    (b) a step of fabricating the first conductive film and the first and the second silicon nitride films into a predetermined pattern, to form a gate electrode of the MISFET,    (c) a step of introducing impurities into the semiconductor substrate in an self-alignment manner to the gate electrode for forming semiconductor regions that function as the source and the drain,    (d) a step of depositing a third silicon nitride film on the gate electrode and a fourth silicon nitride film on the third silicon nitride film,    (e) a step of applying anisotropic etching to the third and the fourth silicon nitride films, to form a side wall spacer on the side wall of the gate electrode,    (f) a step of depositing an oxide film over the gate electrode and the side wall spacer, and    (g) a step of applying etching to the oxide film for forming an opening to the oxide film for exposing a portion of the semiconductor region,    wherein the first silicon nitride film is formed at a temperature lower than that for the second silicon nitride film, and the third silicon nitride film is formed at a temperature lower than that for the fourth silicon nitride film.    
     
     
         21 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 20   , wherein the first and the third silicon nitride films are formed by a plasma CVD method.  
     
     
         22 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 20   , further including a step of depositing a second conductive film in the opening.  
     
     
         23 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 20   , wherein the first conductive film is formed from a refractory metal by a sputtering method.  
     
     
         24 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 23   , further including a step of depositing a polysilicon film and a film for preventing reaction between the polysilicon film and the first conductive film over the semiconductor substrate before forming the first conductive film.  
     
     
         25 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 24   , further including a step of forming a titanium nitride film as the reaction preventive film.  
     
     
         26 . A method of manufacturing a semiconductor integrated circuit device as defined in    claim 20   , further including a step of applying chemical and mechanical polishing to the surface of the oxide film after depositing the oxide film.