Semiconductor integrated circuit and method for generating internal supply voltage in semiconductor integrated circuit

Abstract

The invention aims at securely generating an internal supply voltage when turning on the power supply of internal circuits in a semiconductor integrated circuit where the operation voltage is low, and securely resetting the internal circuits. The voltage generator generates an internal supply voltage supplied to the internal circuits based on the reference voltage by using the external supply voltage supplied from the exterior. That is, the voltage generator forcibly supplies the external supply voltage as internal supply voltage when the power-on reset signal is activated. Therefore, when the external supply voltage is low at the time of turning-on of the power, and the voltage generator does not operate normally, the internal supply voltage can be securely generated following the external supply voltage so as to be supplied to the internal circuits.

What is claimed is:  
     
         1 . A semiconductor integrated circuit comprising: 
 a voltage generator for generating an internal supply voltage supplied to internal circuits based on a reference voltage by using an external supply voltage supplied from an exterior; and    a power-on circuit for inactivating a power-on reset signal which resets at least one of said internal circuits when both said external supply voltage and said internal supply voltage exceed a predetermined value, and wherein    said voltage generator supplies said external supply voltage as said internal supply voltage when said power-on reset signal is activated.    
     
     
         2 . The semiconductor integrated circuit according to    claim 1   , wherein said voltage generator comprises: 
 a differential amplifier for receiving said reference voltage and a voltage that fluctuates depending on said internal supply voltage; and    a regulator controlled on the basis of an output of said differential amplifier for generating said internal supply voltage by using said external supply voltage, and wherein:    said power-on reset signal controls one of said differential amplifier and said regulator; and    said regulator is turned on when said power-on reset signal is activated.    
     
     
         3 . The semiconductor integrated circuit according to    claim 2   , wherein said differential amplifier comprises a CMOS current-mirror circuit.  
     
     
         4 . The semiconductor integrated circuit according to    claim 1   , wherein: 
 said voltage generator comprises a transistor for connecting an external supply line supplied with said external supply voltage, to an internal supply line supplied with said internal supply voltage; and    said transistor is turned on when said power-on reset signal is activated.    
     
     
         5 . The semiconductor integrated circuit according to    claim 1   , comprising a plurality of said voltage generators, and wherein: 
 said power-on circuit comprises a plurality of reset signal generators for inactivating respective reset signals when said external supply voltage exceeds a predetermined value and said internal supply voltage respectively generated by said voltage generators exceeds a predetermined value; and    said power-on reset signal is inactivated in response to said reset signal which has been inactivated latest and is activated in response to said reset signal which has been activated earliest.    
     
     
         6 . The semiconductor integrated circuit according to    claim 5   , wherein at least one of said voltage generators generates said internal supply voltage lower than said external supply voltage; and 
 said power-on circuit comprises:    a logical operation circuit for logically operating values represented by said reset signals to output the operation result as said power-on reset signal; and    a level shifter for receiving said reset signal corresponding to said internal supply voltage lower than said external supply voltage to raise a logic level of said reset signal on the high voltage side and supplying the raised reset signal to said logical operation circuit.    
     
     
         7 . The semiconductor integrated circuit according to    claim 5   , wherein at least one of said voltage generators generates said internal supply voltage lower than said external supply voltage; and 
 said reset signal generator for inactivating said reset signal in accordance with said internal supply voltage lower than said external supply voltage comprise:    a transistor for receiving a control voltage generated by dividing said internal supply voltage with resistance;    a resistor having one end connected with a drain of said transistor and the other end supplied with said external supply voltage, and    wherein said reset signal is generated from a connected node of said transistor and said resistor.    
     
     
         8 . A method for generating internal supply voltage in a semiconductor integrated circuit, comprising the steps of: 
 generating an internal supply voltage supplied to internal circuits based on a reference voltage by using an external supply voltage supplied from an exterior;    inactivating a power-on reset signal which resets at least one of said internal circuits when both said external supply voltage and said internal supply voltage exceed a predetermined value; and    supplying said external supply voltage as said internal supply voltage when said power-on reset signal is activated.    
     
     
         9 . The method for generating internal supply voltage in a semiconductor integrated circuit according to    claim 8   , comprising the steps of: 
 generating a plurality of said internal supply voltages supplied to said internal circuits;    inactivating reset signals respectively corresponding to said external supply voltage and said internal supply voltages when each of said supply voltages respectively exceed a predetermined value; and    inactivating said power-on reset signal in response to said reset signal that has been inactivated latest and activating said power-on reset signal in response to said reset signal that has been activated earliest.