Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem

Abstract

A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (“ROM”) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access (“DMA”) modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.

What is claimed is:  
     
         1 . A computer including at least one data processor for operating on user data in accordance with program instructions, said computer further including at least one memory array presenting a data and address bus, said computer comprising: 
 a memory algorithm processor associated with said memory array and coupled to said data and address buses, said memory algorithm processor being configurable to perform at least one identified algorithm on an operand received from a write operation to said memory array.    
     
     
         2 . The computer of    claim 1    wherein said memory algorithm processor comprises a field programmable gate array.  
     
     
         3 . The computer of    claim 1    wherein said memory algorithm processor is operative to access said memory array independently of said processor.  
     
     
         4 . The computer of    claim 1    wherein said at least one identified algorithm is preprogrammed into said memory algorithm processor.  
     
     
         5 . The computer of    claim 4    wherein said at least one identified algorithm is preprogrammed into a memory device associated with said memory algorithm processor.  
     
     
         6 . The computer of    claim 5    wherein said memory device comprises at least one read only memory device.  
     
     
         7 . The computer of    claim 1    further comprising a first plurality of said data processors and a second plurality of said memory arrays, each of said memory arrays comprising an associated memory algorithm processor.  
     
     
         8 . The computer of    claim 7    wherein a memory algorithm processor associated with a first one of said second plurality of said memory arrays is operative to pass a result of a processed operand to another memory algorithm processor associated with a second one of said second plurality of said memory arrays.  
     
     
         9 . The computer of    claim 1    wherein said memory algorithm processor further comprises: 
 a control block including a command decoder coupled to said address bus and a counter coupled to said command decoder, said command decoder for providing a last operand flag to said counter in response to a last operand command from an operating system of said at least one processor.  
 
     
     
         10 . The computer of    claim 9    wherein said memory algorithm processor further comprises: 
 an equality comparator coupled to receive a pipeline depth signal and an output of said counter for providing a pipeline empty flag to at least one status register.  
 
     
     
         11 . The computer of    claim 10    wherein said status register is coupled to said command decoder to receive a register control signal and a status signal to provide a status word output signal.  
     
     
         12 . A multiprocessor computer including a first plurality of data processors for operating on user data in accordance with program instructions and a second plurality of memory arrays, each presenting a data and address bus, said computer comprising: 
 a memory algorithm processor associated with at least one of said second plurality of memory arrays and coupled to said data and address bus thereof, said memory algorithm processor being configurable to perform at least one identified algorithm on an operand received from a write operation to said associated one of said second plurality of memory arrays.    
     
     
         13 . The multiprocessor computer of    claim 12    wherein said memory algorithm processor associated with one of said second plurality of memory arrays is accessible by more than one of said first plurality of data processors.  
     
     
         14 . The multiprocessor computer of    claim 13    wherein said memory algorithm processor associated with one of said second plurality of memory arrays is accessible by all of said first plurality of data processors.  
     
     
         15 . The multiprocessor computer of    claim 12    wherein said memory algorithm processor comprises: 
 a control block operative to provide a last operand flag in response to a last operand having been processed in said memory algorithm processor.  
 
     
     
         16 . The multiprocessor computer of    claim 12    further comprising: 
 at least one memory device associated with said memory algorithm processor for storing a number of pre-loaded algorithms.  
 
     
     
         17 . The multiprocessor computer of    claim 16    wherein said at least one memory device is responsive to a predetermined command to enable a selected one of said number of pre-loaded algorithms to be implemented by said memory algorithm processor.  
     
     
         18 . The multiprocessor computer of    claim 16    wherein said at least one memory device comprises at least one read only memory device.  
     
     
         19 . The multiprocessor computer of    claim 12    wherein said memory algorithm processor comprises a field programmable gate array.  
     
     
         20 . The multiprocessor computer of    claim 12    wherein said memory algorithm processor is accessible through normal memory access protocol.  
     
     
         21 . The multiprocessor computer of    claim 12    wherein said memory algorithm processor has direct memory access capability to said associated one of said second plurality of memory arrays.  
     
     
         22 . The multiprocessor computer of    claim 12    wherein a memory algorithm processor associated with a first one of said second plurality of said memory arrays is operative to pass a result of a processed operand to another memory algorithm processor associated with a second one of said second plurality of said memory arrays.  
     
     
         23 . The multiprocessor computer of    claim 12    wherein said computer is operative to automatically detect parallel regions of application program code that are capable of being executed in said memory algorithm processor.  
     
     
         24 . The multiprocessor computer of    claim 23    wherein said memory algorithm processor is configurable by said application program code.