Device having metal interconnects with reduced or eliminated metal recess in vias

Abstract

A semiconductor device having metal interconnects provides for a reduction of the recessing of metal in vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The device includes a via in a device layer of the semiconductor device, a barrier layer formed over the device layer, and a metal layer formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

We claim:  
     
         1 . A semiconductor device having a device layer, the semiconductor device comprising: 
 a via in the device layer of the semiconductor device;    a barrier layer over the device layer and over the barrier layer and in the via;    metallic material disposed in the via;    a conductive structure formed over the device layer and in contact with the metallic material, the conductive structure having a sidewall extending from a surface of the barrier layer;    a spacer on the sidewall of the conductive structure; and    wherein the metallic material in the via is protected by a spacer on the sidewall of the conductive structure during a removal of a portion of a conducting barrier adjacent to the via and over the device layer.    
     
     
         2 . The semiconductor device of    claim 1   , wherein the barrier layer extends above and laterally beyond the via.  
     
     
         3 . The semiconductor device of    claim 2   , wherein the metal layer is adapted and configured as a single metal layer that is characterized as contiguously formed in a single deposition step.  
     
     
         4 . The semiconductor device of    claim 1   , wherein the via has a sidewall and a bottom surface and the barrier layer is over the device layer and on the sidewall and the bottom surface of the via.  
     
     
         5 . The semiconductor device of    claim 1   , wherein the barrier layer comprises a conductive material.  
     
     
         6 . The semiconductor device of    claim 1   , wherein the device layer comprises a dielectric material.  
     
     
         7 . The semiconductor device of    claim 1   , wherein the metal layer comprises a metallic material, the metallic material being at least one of aluminum, copper, tungsten, or alloys thereof.  
     
     
         8 . The semiconductor device of    claim 7   , wherein the metal layer comprises an aluminum alloy.  
     
     
         9 . The semiconductor device of    claim 8   , wherein the aluminum alloy comprises an aluminum/copper alloy.  
     
     
         10 . The semiconductor device of    claim 1   , further comprising forming an anti-reflective coating layer over the metal layer.  
     
     
         11 . The semiconductor device of    claim 10   , wherein the anti-reflective coating layer comprises a conductive material.  
     
     
         12 . The semiconductor device of    claim 1   , wherein the conductive structure is formed directly over the via structure.