US2001019180A1PendingUtilityA1
Semiconductor integrated circuit device and process for manufacturing the same
Priority: Dec 27, 1999Filed: Mar 20, 2001Published: Sep 6, 2001
Est. expiryDec 27, 2019(expired)· nominal 20-yr term from priority
H10W 72/5524H10W 72/5522H10W 72/5434H10W 72/5363H10W 72/29H10W 72/59H10W 72/952H10W 72/9232H10W 72/921H10W 72/923H10W 72/983H10W 72/012H10W 72/07533H10W 72/07511H10W 72/252H10W 72/251H10P 14/412H10W 72/5525H10W 72/019H10W 20/084H10W 20/081H10W 20/435H10W 20/425H10W 72/071H10B 12/09H10B 12/48
37
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A semiconductor integrated circuit device comprises a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor integrated circuit device of the type which comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, and a bonding pad formed at an upper wiring layer, further comprising a first interlayer insulating film provided beneath said bonding pad formed, and a first plug formed in said first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in said first interlayer insulating film wherein any wire connected to said first plug is not formed in a wiring layer beneath said first plug.
2 . A semiconductor integrated circuit device according to claim 1 , wherein a wire is formed in a wiring layer lower than the wiring layer beneath said first plug.
3 . A semiconductor integrated circuit device according to claim 1 , wherein any wire is not formed in either of the wiring layers in a lower region of said bonding pad.
4 . A semiconductor integrated circuit device according to claim 1 , wherein said first interlayer insulating film of an element-forming region has a first through-hole, in which a second plug is buried for electric connection between a wire formed in the upper wiring layer and a wire formed in a lower wiring layer, and said first through-hole has a diameter substantially equal to that of said hole.
5 . A semiconductor integrated circuit device according to claim 1 , wherein said first interlayer insulating film of an element-forming region has a first through-hole, in which a second plug is buried for electric connection between a wire formed in the upper wiring layer and a wire formed in a lower wiring layer, and said hole has a depth greater than said first through-hole.
6 . A semiconductor integrated circuit device according to claim 1 , wherein said first conductive film buried in said hole contains a refractory metal film as its main component, and a barrier metal film is formed at the interface between said refractory metal film and the inner walls of said hole.
7 . A semiconductor integrated circuit device according to claim 1 , wherein said bonding pad and said first plug are integrally formed.
8 . A semiconductor integrated circuit device according to claim 1 , wherein said bonding pad has a length of 80 μm or below at one side thereof.
9 . A semiconductor integrated circuit device of the type which comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, a bonding pad formed at an upper wiring layer and connected to a wire, further comprising a first interlayer insulating film provided at a lower region of the wire, and a first plug formed in said first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in said first interlayer insulating film wherein any wire is not formed in a wiring layer below the first plug.
10 . A semiconductor integrated circuit device of the type which comprises a plurality of wiring layers formed on a semiconductor substrate through an interlayer insulating film, and a bonding pad formed at an uppermost wiring layer, further comprising a first interlayer insulating film provided beneath the bonding pad, a first plug formed in said first interlayer insulating film in such a way that a first conductive film is buried in a hole formed in said first interlayer insulating film, and a wire formed in a wiring layer beneath said first plug and made of a third conductive film whose hardness is higher than that of a second conductive film constituting an uppermost wire.
11 . A semiconductor integrated circuit device according to claim 10 , wherein said third conductive film contains copper as its main component.
12 . A semiconductor integrated circuit device according to claim 1 , wherein a wire of the wiring layer beneath said first plug is formed as not to be connected to said first plug in the lower region of said bonding pad.
13 . A method for manufacturing a semiconductor integrated circuit device comprising the steps of:
(a) forming a wire in an element-forming region on a semiconductor substrate and further forming an interlayer insulating film over said wire; (b) etching the first interlayer insulating film in the element-forming region to forma first through-hole reaching said wire, and etching the first interlayer insulating film in a bonding pad-forming region to form a hole; (c) forming a barrier metal film on the first interlayer insulating film including the inner surfaces of said hole and the inner surfaces of said first through-hole and forming a first conductive film containing as its main component a refractory metal film on the upper portion of the barrier metal film so that said first conductive film is buried in the hole and the first through-hole; (d) removing said first conductive film from the upper portion of the first interlayer insulating film by etching to form a first plug constituted of said barrier metal film and said first conductive film in the hole and also a second plug constituted of said barrier metal film and said first conductive film in said first through-hole; and (e) etching a second conductive film formed on the upper portion of said first interlayer insulating film so that an uppermost wire is formed on said first interlayer insulating film in the element-forming region and forming a bonding pad on said first interlayer insulating film in the bonding pad-forming region.
14 . A method for manufacturing a semiconductor integrated circuit device according to claim 13 , further comprising, after the step (e), the steps of bonding a first wire on said bonding pad and bonding a second wire on said first wire.
15 . A method for manufacturing a semiconductor integrated circuit device according to claim 13 , wherein said barrier metal film is made of a multi-layered film of a TiN film formed on a Ti film, said first conductive film includes a W film, and the etching of said first conductive film is carried out in an atmosphere of a gas containing fluorine.Join the waitlist — get patent alerts
Track US2001019180A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.