EEPROM array using 2 bit non-volatile memory cells and method of implementing same

Abstract

An electrically erasable programmable read only memory block is provided which includes a plurality of rows of 2-bit non-volatile memory cells. Each of the memory cells has a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit. Each pair of adjacent memory cells in each row are coupled to share a common diffusion bit line. A plurality of metal bit lines are coupled to the diffusion bit lines through high voltage select transistors. In one embodiment, there are half as many metal bit lines as diffusion bit lines.

1 . An electrically erasable programmable read only memory (EEPROM) block comprising: 
 a row of 2-bit non-volatile memory cells, each of the memory cells having a first charge trapping region for storing a bit and a second charge trapping region for storing a bit, wherein each pair of adjacent memory cells in the row are coupled to share a common diffusion bit line;    a plurality of metal bit lines; and    a plurality of high voltage select transistors coupled between the diffusion bit lines and the metal bit lines.    
     
     
         2 . The EEPROM block of    claim 1   , wherein the row of memory cells comprises a shared memory cell located at each end of the row.  
     
     
         3 . The EEPROM block of    claim 1   , wherein there are half as many metal bit lines as diffusion bit lines.  
     
     
         4 . An electrically erasable programmable read only memory (EEPROM) array comprising: 
 a plurality of rows of 2-bit non-volatile memory cells, each of the memory cells having a first charge trapping region for storing a first bit and a second charge trapping region for storing a second bit; and    a dedicated set of high voltage select transistors coupled to each of said rows of memory cells.