Hybrid BGA and QFP chip package assembly and process for same

Abstract

The present invention provides a hybrid chip package that utilizes a high-speed BGA structure and a plurality of flexible and reliable QFP leads. More specifically, the QFP leads are attached to a peripheral region of a substrate to surround the attached BGA structure and replace solder bumps of a conventional BGA structure that would typically flack or crack during operational cycles to create an electrical open between the conventional BGA package and the attached printed circuit board.

What is claimed is:  
     
         1 . A semiconductor device assembly, comprising: 
 a semiconductor chip;    a ball grid array (“BGA”) structure;    a substrate coupled between the chip and the BGA structure;    a plurality of quad flat panel (“QFP”) leads coupled to said substrate; and    a protective layer bonded to an over the chip and a portion of the substrate adjacent the chip.    
     
     
         2 . The assembly of    claim 1   , wherein said plurality of QFP leads couple to the substrate around a peripheral region surrounding said BGA structure.  
     
     
         3 . The assembly of    claim 1   , wherein said plurality of QFP leads couple to the peripheral edge of said substrate.  
     
     
         4 . The assembly of    claim 1   , wherein said plurality of QFP leads comprises a pin structure selected from the group including I, J, S, or gull wing.  
     
     
         5 . The assembly of    claim 1   , wherein said plurality of QFP leads is gull wing leads.  
     
     
         6 . The assembly of    claim 1   , wherein said QFP leads provide a flexibility to a peripheral region surrounding the BGA substrate to reduce the development of electrical opens while the assembly reacts to operational temperature cycles.  
     
     
         7 . The assembly of    claim 1   , wherein said plurality of conductive bumps being centrally located on said substrate in a predetermined region to reduce the development of electrical opens caused by operational cycles of the assembly.  
     
     
         8 . The assembly of    claim 1   , wherein said plurality of QFP leads provides a pitch of between about 30 to 100 mils.  
     
     
         9 . The assembly of    claim 1   , wherein said BGA structure includes a plurality of conductive bumps distributed in an array over a central portion of said substrate.  
     
     
         10 . The assembly of    claim 9   , wherein said plurality of conductive bumps provide a pitch of about 1.27 mm.  
     
     
         11 . The assembly of    claim 1   , wherein said BGA structure includes an array of conductive bumps, and conductive paste pads between the conductive bumps and the substrate.  
     
     
         12 . The assembly of    claim 1   , wherein said substrate comprises a material selected from the group including BT laminate, FR-4, and cyanate ester.  
     
     
         13 . The assembly of    claim 1   , further including bond wire attached between said chip and said substrate.  
     
     
         14 . A process of fabricating a semiconductor device assembly, comprising: 
 providing a substrate including first and second surfaces;    attaching a plurality of quad flat panel (“QFP”) leads to the substrate on a first surface;    securing a semiconductor chip to a second surface of the substrate;    encapsulating the chip and a portion of the substrate adjacent the chip; and    coupling a ball grid array (“BGA”) structure to the substrate on the first surface.    
     
     
         15 . The process of    claim 14   , wherein attaching a plurality of QFP leads provides a flexibility to a peripheral region surrounding the BGA substrate to reduce the development of electrical opens while the assembly reacts to operational temperature cycles.  
     
     
         16 . The process of    claim 14   , wherein attaching a plurality of QFP leads further includes coupling said plurality of QFP leads to the substrate by a technique selected from the group comprising brazing, embedding, plating, and adhering.  
     
     
         17 . The process of    claim 14   , wherein attaching a plurality of QFP leads further includes adhesively coupling said leads to the first surface of said substrate using a material having conductive properties.  
     
     
         18 . The process of    claim 14   , wherein attaching a plurality of QFP leads further includes tearing the leads around a peripheral region of said BGA structure.  
     
     
         19 . The process of    claim 14   , wherein coupling the BGA structure includes coupling an array of conductive bumps, and conductive paste pads between the conductive bumps and the substrate.  
     
     
         20 . The process of    claim 14   , wherein providing the substrate includes providing a substrate comprised of a material selected from the group including tape, plastic, laminate, and ceramic.  
     
     
         21 . The process of    claim 20   , wherein the substrate is selected from the group including BT laminate, FR-4, and cyanate ester.  
     
     
         22 . The assembly of    claim 14   , further including attaching bond wire between said chip and said substrate.  
     
     
         23 . A chip package assembly being coupled to a printed circuit board (“PCB”), comprising: 
 a semiconductor chip;  
 a ball grid array (“BGA”) structure;  
 a substrate coupled between the chip and the BGA structure;  
 a protective layer encapsulating the chip and a portion of the substrate adjacent the chip; and  
 a plurality of conductive leads electrically coupled between the assembly and PCB that provide a flexible characteristic for accommodating the physical changes that the resultant structure endures during operational cycles.  
 
     
     
         24 . The assembly of    claim 23   , wherein said plurality conductive leads are QFP leads selected from the group including I, J, S, and gull wing.  
     
     
         25 . The assembly of    claim 23   , wherein said plurality of conductive leads couple to the peripheral edge of said substrate to surround the BGA structure.  
     
     
         26 . The assembly of    claim 23   , wherein said plurality of conductive leads forms a tiered structure around the peripheral region surrounding the BGA structure.  
     
     
         27 . The assembly of    claim 23   , wherein said plurality of conductive leads couple to the substrate to surround a peripheral region of the BGA structure.