Trench seimconductor devices reduced trench pitch

Abstract

A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.

What is claimed is:  
     
         1 . A method of reducing the pitch between a pair of trenches formed in a substrate, said method comprising the steps of: 
 patterning a pair of trench opening accesses on said substrate, said pair of trench opening accesses being separated by a mesa definition having a patterned mesa width that is less than a target mesa width;    forming said pair of trenches, through said pair of trench opening accesses and into said substrate, so that said pair of trenches are separated by said patterned mesa width; and    growing a layer of silicon inside said pair of trenches to increase said mesa width to a final mesa width that is greater than or equal to said target mesa width.    
     
     
         2 . The method of    claim 1   , wherein said step of patterning comprises the steps of: 
 growing a hard mask on said surface of said substrate; and    photolithographically defining said pair of trench opening accesses in said hard mask.    
     
     
         3 . The method of    claim 2    wherein said step of forming is performed using an anisotropic etch.  
     
     
         4 . The method of    claim 3   , further comprising a step of annealing walls of said pair of trenches using hydrogen gas, prior to said step of growing a layer of silicon, to reduce a defect density on said walls of said pair of trenches and to cause upper and lower corners at the tops and bottoms of said pair of trenches to become rounded.  
     
     
         5 . The method of    claim 4   , wherein said step of annealing is performed within a temperature range of about 960 to 1160° C. and within a pressure range of about 40 to 240 Torr.  
     
     
         6 . The method of    claim 5   , wherein said method is used to fabricate a trench field effect transistor.  
     
     
         7 . A method of making a trench field effect transistor, comprising the steps of: 
 providing a semiconductor substrate of a first dopant charge type,    growing a base silicon layer of the same first dopant charge type on said substrate;    forming two or more trenches into said base silicon layer, each trench defined by a first end in a plane defined by a major surface of said substrate and by walls extending to a second end at a first predetermined depth into said base silicon layer, wherein mesas separating adjacent trenches have initial widths that are smaller than a target width; and    growing a second layer of silicon on said walls of said trenches and said mesas so that said mesa widths conform to a final width that is greater than or equal to said target width.    
     
     
         8 . The method of    claim 7   , further comprising the step of: 
 annealing said trenches, prior to said step of growing a second layer of silicon, to: 
 reduce the number of defects on said walls of said trenches, and  
 round corners at said first and second ends of said trenches.  
   
     
     
         9 . The method of    claim 8   , wherein said annealing step is performed using hydrogen gas, within a temperature range of 960 to 1160° C., and within a pressure range of 40 to 240 Torr.  
     
     
         10 . The method of    claim 9   , further comprising the steps of: 
 growing a dielectric layer over said second layer of silicon;    forming a conductor over said dielectric layer, said conductor embodying the gate of said trench field effect transistor;    patterning and implanting a dopant of a second charge type to form wells interposed between said trenches; and    patterning and implanting a dopant of said first charge type to form regions that embody the source regions of said field effect transistor.    
     
     
         11 . A trench field effect transistor, comprising: 
 a semiconductor substrate of a first dopant charge type, said substrate embodying the drain of said trench field effect transistor;    a body layer of a second dopant charge type, formed over a major surface of said substrate;    at least two or more trenches defined by walls extending through said body layer and into said substrate to a trench termination depth, the trenches having first ends at a major surface of the body layer and a second end at said trench termination depth;    a layer of silicon covering said walls of said at least one trench;    a dielectric layer covering inner walls of said layer of silicon;    a conductor covering inner walls of said dielectric layer, said conductor embodying the gate of said trench field effect transistor; and    source regions of said first dopant charge type flanking outer walls of said dielectric layer and extending from said major surface of said body layer to a first predetermined depth within said body layer.    
     
     
         12 . The field effect transistor of    claim 11   , further comprising a heavy body layer of said second dopant charge type interposed between said source regions and recessed to a second predetermined depth within said body layer, said heavy body layer having a doping concentration that is higher than a doping concentration of said body layer.  
     
     
         13 . A method of making a trench field effect transistor, comprising the steps of: 
 providing a semiconductor substrate of a first dopant charge type,    growing a base silicon layer of the same first dopant charge type on said substrate;    forming two or more trenches into said base silicon layer, each trench defined by a first end in a plane defined by a major surface of said substrate and by walls extending to a second end at a first predetermined depth within said base silicon layer, wherein mesas separating adjacent trenches have initial widths that are smaller than a minimum allowable mesa width;    annealing said trenches, prior to said step of growing a layer of silicon in order to:    reduce the number of defects on said walls of said trenches, and    round corners at said first and second ends of said trenches;    growing a second layer of silicon on said walls of said trenches and on said mesas between said trenches so that said mesa widths conform to a final width that is approximately greater than or equal to said minimum allowable mesa width;    growing a dielectric layer over said second layer of silicon;    forming a conductive layer over said dielectric layer, said conductive layer embodying the gate of said trench MOSFET;    patterning and implanting a dopant of a second charge type to form wells interposed between trenches; and    patterning and implanting a dopant of said first charge type to form regions that embody the source regions of said MOSFET.    
     
     
         14 . The method of    claim 13   , wherein said annealing step is performed using hydrogen gas, within a temperature range of 960 to 1160° C., and within a pressure range of 40 to 240 Torr.  
     
     
         15 . A method of forming two or more trenches that are separated by mesas in a substrate, said method comprising the step of: 
 growing a layer of silicon on walls that define the trenches so that the width of said mesas is increased from a width below a target mesa dimension to a width that is greater than or equal to said target mesa dimension.