Field-effect transistor and method for manufacturing the field effect transistor

Abstract

A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N 2 and thickness D of the second conductivity layer are such that the following relationship holds: d > 2  ɛ S  φ S eN 2 + 2  ɛ S  V bi eN 2  N 1 N 1 + N 2 wherein N 1 is the impurity concentration of the first conductivity epitaxial layer, Ø S , ∈ S and V bi , are surface potential, dielectric constant and a diffused potential, respectively, of the second conductivity epitaxial layer, and e is an elementary charge of electron. An electrically neutral region is formed in the second conductivity epitaxial layer when no voltage is applied between the gate and the source region, whereby the electrically neutral region functions similarly to the gate of a cascode-connected MOSFET, which improves the breakdown voltage of the FET.

What is claimed is:  
     
         1 . A field effect transistor (FET) comprising a substrate, a first epitaxial layer overlying said substrate and having a first conductivity, a second epitaxial layer formed on said first epitaxial layer and having a second conductivity, source and drain regions in ohmic contact with said second epitaxial layer, and a gate metal formed on said second epitaxial layer in Schottky contact therewith, said second epitaxial layer having an impurity concentration and a thickness such that an electrically neutral region is formed when said gate metal has a potential substantially equal to a potential of said drain region.  
     
     
         2 . The FET as defined in    claim 1   , wherein said gate metal has a bottom surface in contact with said second epitaxial layer.  
     
     
         3 . The FET as defined in    claim 1   , wherein said gate metal penetrates said second epitaxial layer to electrically contact said first epitaxial layer.  
     
     
         4 . The FET as defined in    claim 3   , wherein said gate metal has a step portion from which a tip portion of said gate metal protrudes, said step portion has a bottom surface abutting said second epitaxial layer, and said tip portion abuts said first epitaxial layer.  
     
     
         5 . The FET as defined in    claim 1   , wherein said second epitaxial layer has an opening between said gate metal and said source region, and said gate metal has a bottom abutting said first epitaxial layer.  
     
     
         6 . The FET as defined in    claim 1   , wherein said second epitaxial layer has an opening exposing a portion of said first epitaxial layer located between said gate electrode and said drain region.  
     
     
         7 . The FET as defined in    claim 1   , wherein the following relationship holds:  
       
         
           
             
               d 
               > 
               
                 
                   
                     
                       2 
                        
                       
                         ɛ 
                         S 
                       
                        
                       
                         φ 
                         S 
                       
                     
                     
                       eN 
                       2 
                     
                   
                 
                 + 
                 
                   
                     
                       
                         2 
                          
                         
                           ɛ 
                           S 
                         
                          
                         
                           V 
                           bi 
                         
                       
                       
                         eN 
                         2 
                       
                     
                      
                     
                       
                         N 
                         1 
                       
                       
                         
                           N 
                           1 
                         
                         + 
                         
                           N 
                           2 
                         
                       
                     
                   
                 
               
             
           
           
           
               
           
         
         wherein N 1  is an impurity concentration of said first epitaxial layer, wherein Ø S , ∈ S  V bi , N2 and d are surface potential, dielectric constant, a diffused potential, an impurity concentration and thickness, respectively, of said second epitaxial layer, and wherein e is an elementary charge of electron.  
       
     
     
         8 . A method for fabricating a field effect transistor comprising the steps of depositing a first epitaxial layer having a first conductivity and overlying a substrate, depositing a second epitaxial layer having a second conductivity on said first epitaxial layer, forming an ohmic layer on said second epitaxial layer, forming an ohmic layer having a first conductivity on said second epitaxial layer, forming a gate in Schottky contact with said second epitaxial layer and source and drain regions on said ohmic layer, and selectively etching said second epitaxial layer to form an opening for exposing a portion of said first epitaxial layer by using an etchant, said etchant and a semiconductor material of said epitaxial layer being selected such that an etch rate of said second epitaxial layer is lower than an etch rate of said ohmic layer.  
     
     
         9 . The method as defined in    claim 8   , further comprising the steps of selectively etching portions of said ohmic layer corresponding to said source and drain regions and filling said etched portions with an ohmic metal.