Semiconductor device having a recessed gate structure and method of manufacturing the same

Abstract

A method of forming a semiconductor device on a substrate comprising the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

What is claimed is:  
     
         1 . A method of forming a semiconductor device on a substrate, comprising the steps of: 
 forming a first recess in the substrate;    depositing an insulator on the substrate and in the first recess so that an isolation region is formed when the first recess is filled with the insulator;    forming a second recess in a predetermined area of the substrate and in the insulator disposed over the predetermined area;    forming a recess insulation layer on the surface of the second recess;    depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material;    removing a sufficient amount of the insulator and the conductive material so that top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.    
     
     
         2 . A method according to    claim 1    wherein the step of forming the first recess comprises: 
 etching the substrate with a plasma of etchant gas.  
 
     
     
         3 . A method according to    claim 2    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         4 . A method according to    claim 1    wherein the step of forming the second recess comprises: 
 etching the predetermined area of the substrate with a plasma of etchant gas.  
 
     
     
         5 . A method according to    claim 4    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         6 . A method according to    claim 1    wherein the step of depositing the conductive material is performed by chemical vapor deposition.  
     
     
         7 . A method according to    claim 1    wherein the step of removing the sufficient amount of the insulator and the conductive material comprises the steps of: 
 etching the insulator and the conductive material with a plasma of etchant gas; and  
 planarizing the top surface of the insulator and the top surface of the conductive material.  
 
     
     
         8 . A method according to    claim 7    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         9 . A method according to    claim 1    wherein the step of planarizing comprises: 
 performing chemical mechanical polishing on the top surface of the insulator and the top surface of the conductive material.  
 
     
     
         10 . A method according to    claim 9    wherein the top surface of the insulator and the top surface of the conductive material are polished concurrently.  
     
     
         11 . A method according to    claim 1    wherein the recess insulation layer comprises TEOS.  
     
     
         12 . A method according to    claim 1    further comprising: 
 doping the gate region and at least one source/drain region near the gate region after the planarizing step.  
 
     
     
         13 . A method according to    claim 12    further comprising: 
 forming a contact on the source/drain region after the doping step.  
 
     
     
         14 . A method of forming a forming a semiconductor device on a substrate having a top surface, comprising the steps of: 
 forming an isolation region containing an insulator in the substrate and a recessed conductor insulated from and disposed within the substrate, said step of forming leaving residual materials disposed above said substrate; and    removing said residual materials so that said insulator and said conductor are substantially aligned with the top surface of the substrate.    
     
     
         15 . A method according to    claim 14    wherein said step of forming comprises the steps of: 
 forming a protective layer on the top surface of the substrate;  
 forming a first recess in a first predetermined region of the substrate including removing the protective layer above the first predetermined region of the substrate;  
 forming the isolation region insulator above the protective layer and in the first recess so that a top portion of the isolation region insulator is formed at least up to a level aligned with the top surface of the substrate;  
 forming a second recess in a second predetermined region of the substrate including removing the protective layer and the isolation region insulator above the second predetermined region of the substrate;  
 forming a recess insulation layer above the insulator and on the surface of the second recess;  
 forming a conductive material on the recess insulation layer and in the second recess so that a top portion of the conductive material is formed at least up to a level aligned with the top surface of the substrate; and  
 wherein the step of removing removes a sufficient amount of the isolation region insulator, the recess insulation layer and the conductive material so that their remains a top surface of the insulator and a top surface of the conductive material that are substantially aligned with the top surface of the substrate.  
 
     
     
         16 . A method according to    claim 15    wherein the step of forming the first recess comprises: 
 etching the substrate and the protective layer with a plasma of etchant gas.  
 
     
     
         17 . A method according to    claim 16    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         18 . A method according to    claim 15    wherein the step of forming the second recess comprises: 
 etching the substrate, the protective layer and the insulator with a plasma of etchant gas.  
 
     
     
         19 . A method according to    claim 18    wherein the plasma of etchant gas comprises.  
     
     
         20 . A method according to    claim 15    wherein the step of removing the sufficient amount of the insulator and the conductive material comprises the steps of: 
 etching the insulator and the conductive material with a plasma of etchant gas; and  
 planarizing the top surface of the insulator and the top surface of the conductive material.  
 
     
     
         21 . A method according to    claim 20    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         22 . A method according to    claim 21    wherein step of planarizing comprises: 
 performing chemical mechanical polishing on the top surfaces of the insulator and the conductive material.  
 
     
     
         23 . A method according to    claim 15    further comprising: 
 doping the conductive material in the second recess and a predetermined region in the substrate near the second recess after the step of planarizing.  
 
     
     
         24 . A method according to    claim 15    further comprising: 
 removing the protective layer after the step of planarizing.  
 
     
     
         25 . A semiconductor device produced in accordance with the method of    claim 15   .  
     
     
         26 . A method of forming an electrical device on an active area of a substrate having a top surface, the active area being within an isolation region in the substrate, the isolation region containing an insulator, the method comprising the steps of: 
 etching a trench in a predetermined area in the substrate within the isolation region;    forming an insulating layer on the surface of the trench;    forming a conductive layer on top of the insulating layer and in the trench so that a top portion of the conductive layer is formed at least up to a level aligned with the top surface of the substrate; and    removing a sufficient amount of the insulator and the conductive layer so that the top surface of the conductive layer is at a level that is substantially aligned with the top surface of the substrate.    
     
     
         27 . A method according to    claim 26    wherein the step of etching the trench comprises: 
 using a plasma of Cl2 or HBr gas to etch the trench.  
 
     
     
         28 . A method according to    claim 26    wherein the step of removing the sufficient amount of the insulator and the conductive layer comprises the steps of: 
 etching the insulator and the conductive layer with a plasma of etchant gas; and  
 planarizing the top surface of the insulator and the top surface of the conductive layer.  
 
     
     
         29 . A method according to    claim 28    wherein the plasma of etchant gas comprises Cl 2 , CHF 3 , CF 4 , HBr or Ar.  
     
     
         30 . A method according to    claim 28    wherein the step of planarizing comprises: 
 performing chemical mechanical polishing on the top surfaces of the insulator and the conductive layer.  
 
     
     
         31 . An electrical device produced in accordance with the method of    claim 26   .  
     
     
         32 . A semiconductor device formed on a semiconductor substrate having a top surface, comprising: 
 an isolation region formed of an insulator within the semiconductor substrate, the isolation region including a top surface;    a recessed conductor formed of a conductive material within the isolation region and in the semiconductor substrate, the recessed conductor including a top surface, the top surface of the recessed conductor being substantially aligned with the top surface of the semiconductor substrate;    a semiconductor region formed in the semiconductor substrate and disposed between the isolation region and the recessed conductor; and    an insulator disposed between said recessed conductor and said semiconductor region.    
     
     
         33 . A semiconductor device according to    claim 32    wherein the top surface of the isolation region is substantially at the same level as the top surface of the semiconductor substrate.  
     
     
         34 . A semiconductor device according to    claim 32    wherein the recessed conductor has a thickness of 2500 Angstroms.  
     
     
         35 . A semiconductor device according to    claim 32    wherein the conductive material within the semiconductor substrate comprises amorphous polysilicon implanted subsequently.  
     
     
         36 . A semiconductor device according to    claim 35    wherein the insulation layer within the semiconductor substrate comprises TEOS.  
     
     
         37 . A semiconductor device according to    claim 32    wherein said semiconductor region is conductive, and said semiconductor region, said insulator and said recessed conductor form a capacitor.  
     
     
         38 . A semiconductor device according to    claim 32    wherein said semiconductor region is doped to form a source and a drain, and said doped semiconductor region, said insulator, and said recessed conductor form a transistor.