Software tool to allow field programmable system level devices

Abstract

A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.

We claim:  
     
         1 . A method for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit, comprising the steps of: 
 simulating in hardware a FPSLIC device;    generating, from the simulation in hardware, a simulator-port layout of the FPSLIC device;    simulating, with an instruction-set simulator, in software the FPSLIC device;    outputting register contents from the instruction-set software, from the simulation in software; and    verifying contents from the simulator-port layout with the register contents.    
     
     
         2 . The method as set forth in    claim 1   , further including the steps of: 
 outputting peripheral contents from the instruction-set simulator, from the simulation in software; and    verifying contents from the simulator-port layout with the peripheral contents.    
     
     
         3 . The method as set forth in    claim 1   , further including the steps of: 
 outputting UART contents from the instruction-set simulator, from the simulation in software; and    verifying contents from the simulator-port layout with the UART contents.    
     
     
         4 . A system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit, comprising: 
 a hardware simulator for simulating a FPSLIC device, with the hardware simulator having a simulator-port layout of the FPSLIC device;    a software simulator for simulating the FPSLIC device, with software simulator having an instruction-set simulator for outputting register contents; and    verification software for verifying contents from the simulator-port layout with the register contents.    
     
     
         5 . The system as set forth in    claim 4   , with: 
 said instruction-set simulator outputting peripheral contents; and    said verification software for verifying contents from the simulator-port layout with the peripheral contents.    
     
     
         6 . The system as set forth in    claim 4   , with: 
 said instruction-set simulator outputting UART contents; and    said verification software for verifying contents from the simulator-port layout with the UART contents.