Processor with reconfigurable arithmetic data path

Abstract

A reconfigurable processor includes at least three (3) MacroSequencers ( 10 )-( 16 ) which are configured in an array. Each of the MacroSequencers is operable to receive on a separate one of four buses ( 18 ) an input from the other three MacroSequencers and from itself in a feedback manner. In addition, a control bus ( 20 ) is operable to provide control signals to all of the MacroSequencers for the purpose of controlling the instruction sequence associated therewith and also for inputting instructions thereto. Each of the MacroSequencers includes a plurality of executable units having inputs and outputs and each for providing an associated execution algorithm. The outputs of the execution units are input to an output selector which selects the outputs for outputs on at least one external output and on at least one feedback path. An input selector ( 66 ) is provided having an input for receiving at least one external output and at least the feedback path. These are selected between for input to select ones of the execution units. An instruction memory ( 48 ) contains an instruction word that is operable to control configurations of the datapath through the execution units for a given instruction cycle. This instruction word can be retrieved from the instruction memory ( 48 ), the stored instructions therein sequenced through to change the configuration of the datapath for subsequent instruction cycles.

What is claimed is:  
     
         1 . A method of floating point mantissa multiplication during two pipeline operations comprising the steps of: 
 generating partial product signals from a plurality of arithmetic data signals representing mantissas of numbers to be multiplied; adding the partial product signals using a multiple-level adder tree to generate a product signal representing the product of the arithmetic data signals at an output level of the adder tree; accumulating in first pipeline registers intermediate level signals output from one level of the adder tree for input to a subsequent level of the adder tree; wherein a first pipeline operation comprising generating said partial product signals and accumulating said intermediate level signals in said first pipeline registers is carried out in one clock cycle;    accumulating in second pipeline registers output signals from a further adder comprising local carry propagate adder cells; selectively feeding back to an input of said further adder signals representing a constant or the contents of at least some of said second pipeline registers; and supplying said product signal as another input to said further adder; wherein said inputs to said further adder are aligned with the precision components of a output signal from said further adder stored by said second pipeline registers; and wherein the signal alignment, storage of said output signal from said further adder in said second pipeline registers, and said selective feedback are effected during a single clock cycle subsequent to said one clock cycle.    
     
     
         2 . A method according to claim  29 , wherein said arithmetic data signals comprise sets of signals representing modular components of relatively small moduli, and multiplication of two or more of said sets of signals are effected during the same clock cycle.  
     
     
         3 . A method according to claim  29 , wherein single precision floating point mantissa multiplication of two m-bit arithmetic data signals is effected in the same clock cycle.  
     
     
         4 . A method according to claim  29 , wherein double precision floating point mantissa multiplication of two m-bit arithmetic data signals is effected in the same clock cycle.  
     
     
         5 . A method according to claim  29 , wherein the arithmetic data signals represent a p-bit number and a q-bit number, respectively, where p and q are sub-multiples of m, and wherein multiplication of two m-bit mantissas is effected during a sequence of clock cycles.  
     
     
         6 . A method according to claim  29 , wherein the arithmetic data signals represent two floating point numbers, and wherein the mantissa of one of said numbers may selectively be replaced by a constant or by a further floating point mantissa derived from the second pipeline registers.