Memory

Abstract

Serial bus modules with unique multibit identifications that may be searched with multiple modules on a single bus. Modules may contain temperature history per integrated Arrhenius temperature dependent signal. Modules may be packaged as tokens or as two or three lead plastic plastic, also with the three lead packages further functionality as sensors or switches may be incorporated into the modules.

What is claimed is:  
     
         1 . A serial-port memory; comprising: 
 (a) a serial port;    (b) a scratchpad memory coupled to said serial port;    (c) a second memory coupled to said scratchpad memory; and    (d) control logic coupled to said serial port and said scratchpad and second memories, said control logic transfers information from said scratchpad memory to said second memory as a block pursuant to a block transfer command received at said serial port.    
     
     
         2 . The memory of  claim 1 , wherein: 
 (a) said serial port, scratchpad memory, second memory, and control logic are in a package with only two electrical contacts.    
     
     
         3 . The memory of  claim 2 , wherein: 
 (a) said package is a token-shaped container with the two planar surfaces providing said two electrical contacts.    
     
     
         4 . The memory of  claim 1 , wherein: 
 (a) said control logic only transfers information to said second memory after a password identifying said second memory has been received at said serial port.    
     
     
         5 . The memory of  claim 1 , wherein: 
 (a) said control logic includes a cyclic redundancy check generator.    
     
     
         6 . The memory of  claim 1 , further comprising: 
 (a) third and fourth memories coupled to said scratchpad memory; and    (b) wherein said control logic transfers information as a block from said scratchpad memory to one of said second, third, and fourth memories pursuant to a block transfer command received at said serial port.    
     
     
         7 . A system with identifiable modules on a serial bus, comprising: 
 (a) a bus master;    (b) a serial bus coupled to said bus master;    (c) a plurality of modules, each of said modules coupled to said bus, and each of said modules having a unique n-bit identification.    (d) each of said modules having control logic programmable to respond to a command sequence of first read, second read, write on said bus from said bus master by (i) responding to said first read by signalling to said bus a jth bit of said identification, (ii) responding to said second read by signalling to said bus the complement of said jth bit, and (iii) responding to said write by comparing said write's bit to said jth bit and (A) when said write's bit differs from said jth bit, then idling said module or (B) when said write's bit matches said jth bit, then incrementing to the j+1)st bit of said identification if j is less than n.    
     
     
         8 . The system of  claim 7 , wherein: 
 (a) said n-bit identification has 64 bits; and    (b) when 64 iterations of the command sequence first read, second read, and write of step (d) of  claim 7  yield  64  consecutive write's bit matching the corresponding identification bit of a first module, said bus master can program a command into said control logic of said first module.    
     
     
         9 . The system of  claim 7 , wherein: 
 (a) each of said modules having control logic programmable to respond to a command write on said bus from said bus master by comparing said write's bit to said jth bit and (A) when said write's bit differs from said jth bit, then idling said module or (B) when said write's bit matches said jth bit, then incrementing to the (j+1)st bit of said identification if j is less than n.    
     
     
         10 . The system of  claim 9 , wherein: 
 (a) said n-bit identification has 64 bits; and    (b) when 64 iterations of the command write of step (a) of  claim 9  yield 64 consecutive write's bit matching the corresponding identification bit of a first module, said bus master can program a command into said control logic of said first module.    
     
     
         11 . The system of  claim 7 , wherein: 
 (a) each of said modules having control logic programmable to respond to a command read on said bus from said bus master by signalling the jth bit of said n-bit identification and then incrementing to the (j+1)st bit of said identification if j is less than n.    
     
     
         12 . The system of  claim 11 , wherein: 
 (a) said n-bit identification has 64 bits; and    (b) when 64 iterations of the command read of step (a) of  claim 11  said bus master can program a command into said control logic of said first module.    
     
     
         13 . A temperature sensor, comprising: 
 (a) a device which provides a signal depending upon absolute temperature T substantially proportional to exp(−Tc/T) where Tc is a constant;    (b) an integrator which samples said signal and accumulates said samples;    (c) an output coupled to said integrator.    
     
     
         14 . The temperature sensor of  claim 13 , wherein: 
 (a) said signal includes the current through a p-n junction; and    (b) said integrator includes a current-to-frequency converter which drives a counter.    
     
     
         15 . The sensor of  claim 13 , wherein: 
 (a) said constant Tc is programmable.