Method for reducing thermal budget in node contact application

Abstract

A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provide, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

What is claimed is:  
     
         1 . A method for forming a structure in an embedded dynamic random access memory, comprising: 
 providing a substrate having a logic region and a memory region;    forming gate structures on said logic region and said memory region;    forming a first inter-poly dielectric layer on surfaces of said gate structures and said substrate;    forming an opening, over said memory region, through said first inter-poly dielectric layer to top surface of said substrate;    forming a conductor on said first inter-poly dielectric layer and to fill said opening;    forming a bit line using photolithography and etching said conductor;    forming a second inter-poly dielectric layer on said first inter-poly dielectric layer and said bit line;    forming a node contact opening through said first inter-poly dielectric layer and said second inter-poly dielectric layer to top surface of said substrate; and    forming a silicon nitride layer on inside wall of said node contact opening by rapid thermal chemical vapor deposition (RTCVD).    
     
     
         2 . The method according to  claim 1 , wherein each of said gate structures comprises a gate oxide, a gate conductor over said gate oxide, a cap isolator over said gate conductor, and a spacer against said gate conductor.  
     
     
         3 . The method according to  claim 1 , wherein said first inter-poly dielectric layer comprises oxide.  
     
     
         4 . The method according to  claim 1 , wherein said conductor filling said opening comprises poly-silicon or polycide.  
     
     
         5 . The method according to  claim 1 , wherein said second inter-poly dielectric layer comprises oxide.  
     
     
         6 . The method according to  claim 1 , wherein said second inter-poly dielectric layer comprises silicon nitride.  
     
     
         7 . The method according to  claim 1 , wherein said seoncd inter-poly dielectric layer comprises a combination layer including a first oxide layer, a nitride layer, and a second oxide layer.  
     
     
         8 . The method according to  claim 1 , wherein said node contact opening is formed by the following steps: 
 coating said second inter-poly dielectric layer with a photoresist layer;    patterning said photoresist layer by exposure and development;    etching said second inter-poly dielectric layer and said first inter-poly dielectric layer, until top surface of said substrate exposed, using said photoresist layer as a mask; and    removing said photoresist layer.    
     
     
         9 . The method according to  claim 1 , wherein the rapid thermal chemical vapor deposition is implemented for about 1 to 2 minutes.  
     
     
         10 . The method according to  claim 1 , wherein the rapid thermal chemical vapor deposition is implemented under the condition of about 500 to 800° C. in temperature.  
     
     
         11 . The method according to  claim 1 , wherein said silicon nitride layer has a thickness of about 300 to 400 angstroms.  
     
     
         12 . A method for forming structure of a semiconductor device, comprising: 
 providing a substrate;    forming a dielectric layer over said substrate;    forming a node contact opening through said dielectric layer to top surface of said substrate by following steps: 
 coating said dielectric layer with a photoresist layer,  
 patterning said photoresist layer with pattern of a node contact by exposure and development,  
 etching said dielectric layer until top surface of said substrate exposed, using said patterned photoresist layer as a mask, and  
 removing said photoresist layer; and  
   forming a silicon nitride layer on inside wall of said node contact opening by rapid thermal chemical vapor deposition (RTCVD).    
     
     
         13 . The method according to  claim 12 , wherein said dielectric layer comprises oxide.  
     
     
         14 . The method according to  claim 12 , wherein said dielectric layer comprises silicon nitride.  
     
     
         15 . The method according to  claim 12 , wherein said dielectric layer comprises a combination layer including a first oxide layer, a nitride layer, and a second oxide layer.  
     
     
         16 . The method according to  claim 12 , wherein the rapid thermal chemical vapor deposition is implemented for about 1 to 2 minutes.  
     
     
         17 . The method according to  claim 12 , wherein the rapid thermal chemical vapor deposition is implemented under the condition of about 500 to 800° C. in temperature.  
     
     
         18 . The method according to  claim 12 , wherein said silicon nitride layer has a thickness of about 300 to 400 angstroms.