Method and apparatus for efficient loading and storing of vectors

Abstract

A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.

What is claimed is:  
     
         1 . A method of loading a vector from memory, comprising: 
 providing a vector in memory; and    embedding a location identifier in bits comprising a vector load instruction, wherein the location identifier indicates an ending location in the vector where useful data ends.    
     
     
         2 . The method of  claim 1 , further including using the location indicator when executing the vector load instruction to load only the useful data from the vector into a vector register.  
     
     
         3 . The method of  claim 2 , further including setting remaining locations in the vector register beyond the useful data to a constant.  
     
     
         4 . The method of  claim 3 , further including providing a constant in the vector load instruction for use in setting the remaining locations in the vector to the constant.  
     
     
         5 . The method of  claim 1 , further including providing dedicated bits in the vector load instruction which provide the location identifier.  
     
     
         6 . The method of  claim 5 , wherein a dimension of the vector is 2 n , and further including providing n bits in the vector load instruction to provide the location identifier.  
     
     
         7 . The method of  claim 1 , further including using the vector load instruction in a data processor having a paired singles execution unit, wherein two single precision values constitute the vector.  
     
     
         8 . A method of storing a vector from a vector register to memory, comprising: 
 providing the vector in a vector register; and    embedding a location identifier in bits comprising a vector store instruction, wherein the location identifier indicates a location in the vector register where useful data ends.    
     
     
         9 . The method of  claim 8 , further including using the location identifier when executing the vector store instruction to store only the useful data in the vector register to memory.  
     
     
         10 . The method of  claim 8 , further including providing dedicated bits in the vector store instruction which provide the location identifier.  
     
     
         11 . The method of  claim 10 , wherein a dimension of the vector is 2 n , and further including providing n bits in the vector store instruction to provide the location identifier.  
     
     
         12 . The method of  claim 8 , further including using the vector store instruction in a data processor having a paired singles execution unit, wherein two single precision values constitute the vector.  
     
     
         13 . A data processor, comprising a vector processing unit, a vector register file, a load/store unit and an instruction set, wherein the instruction set includes at least one vector load instruction having a bit format in which an ending location of useful data within the vector is embedded.  
     
     
         14 . The data processor of  claim 13 , wherein the vector load instruction further includes bits which provide a constant to be used by the load/store unit to set locations in a vector register file beyond the useful data to the constant.  
     
     
         15 . The data processor of  claim 13 , wherein at least one dedicated bit is provided in the bit format of the instruction to provide the ending location of the useful data within the vector.  
     
     
         16 . The data processor of  claim 15 , wherein the vector has a dimension of 2 n  and n dedicated bits are provided in the instruction to provide the ending, location of the useful data.  
     
     
         17 . The data processor of  claim 13 , wherein the vector has a dimension of two.  
     
     
         18 . The data processor of  claim 13 , wherein the vector processing unit is a paired singles unit which processes two single-precision floating point values in parallel.  
     
     
         19 . A data processor, comprising a vector processing unit, a vector register file, a load/store unit and an instruction set, wherein the instruction set includes at least one vector store instruction having a bit format in which an ending location of useful data within the vector is embedded.  
     
     
         20 . The data processor of  claim 19 , wherein at least one dedicated bit is provided in the bit format of the instruction to provide the ending location of the useful data within the vector.  
     
     
         21 . The data processor of  claim 20 , wherein the vector has a dimension of 2 n  and n dedicated bits are provided in the instruction to provide the ending location of the useful data.  
     
     
         22 . The data processor of  claim 19 , wherein the vector has a dimension of two.  
     
     
         23 . The data processor of  claim 19 , wherein the vector processing unit is a paired singles unit which processes two single-precision floating point values in parallel.  
     
     
         24 . A vector load instruction for a data processor, comprising a bit format which includes bits designating a source address where a vector is located, at least one bit which indicates an ending location of useful data within the vector, a value field which provides a constant for use in loading destination vector register locations beyond the useful data, and a destination vector register to be loaded.  
     
     
         25 . The vector load instruction of  claim 24 , wherein the dimension of the vector is 2 n , and n bits are provided in the instruction for indicating the ending location of the useful data within the vector.  
     
     
         26 . A vector store instruction for a data processor, comprising a bit format which includes bits designating a source register containing a vector, at least one position bit which indicates an ending location of useful data within the vector, and a destination address for the vector.  
     
     
         27 . The vector store instruction of  claim 26 , wherein the dimension of the vector is 2 n , and n bits are provided in the instruction for indicating the ending location of the useful data within the vector.  
     
     
         28 . An information processor, including a decoder for decoding instructions including at least some graphics instructions and at least one paired singles instruction, wherein the decoder is operable to decode a 32-bit paired-singlequantized-load instruction, wherein bits  0 - 5  encode a primary op code of 56, bits  6 - 10  designate a floating point destination register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be loaded, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access.  
     
     
         29 . An information processor, including a decoder for decoding instructions including at least some graphics instructions and at least one paired singles instruction, wherein the decoder is operable to decode a 32-bit paired-single-quantized-store instruction, wherein bits  0 - 5  encode a primary op code of 60, bits  6 - 10  designate a floating point source register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be stored, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access.  
     
     
         30 . A decoder for decoding instructions including at least some graphics instructions, wherein the decoder is operable to decode: 
 a 32-bit paired-single-quantized-load instruction, wherein bits  0 - 5  encode a primary op code of 56, bits  6 - 10  designate a floating point destination register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be loaded, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access; and    a 32-bit paired-single-quantized-store instruction, wherein bits  0 - 5  encode a primary op code of 60, bits  6 - 10  designate a floating point source register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be stored, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access.    
     
     
         31 . A storage medium storing a plurality of instructions including at least some graphics instructions and a 32-bit paired-single-quantized-load instruction, wherein bits  0 - 5  encode a primary op code of 56, bits  6 - 10  designate a floating point destination register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be loaded, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access  
     
     
         32 . A storage medium storing a plurality of instructions including at least some graphics instructions and a 32-bit paired-single-quantized-store instruction, wherein bits  0 - 5  encode a primary op code of 60, bits  6 - 10  designate a floating point source register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be stored, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access.  
     
     
         33 . A storage medium storing a plurality of instructions including at least some graphics instructions and: 
 a 32-bit paired-single-quantized-load instruction, wherein bits  0 - 5  encode a primary op code of 56, bits  6 - 10  designate a floating point destination register, bits  11 - 15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be loaded, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access; and    a 32-bit paired-single-quantized-store instruction, wherein bits  0 - 5  encode a primary op code of 60, bits  6 - 10  designate a floating point source register, bits  11  -  15  specify a general purpose register to be used as a source, bit  16  indicates whether one or two paired singles register are to be stored, bits  17 - 19  specify a graphics quantization register (GQR) to be used by the instruction, and bits  20 - 31  provide an immediate field specifying a signed two's compliment integer to be summed with the source to provide an effective address for memory access.