Method and apparatus for biasing radio frequency power transistors

Abstract

The present invention provides a biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortion without affecting the transistor input or output impedance or any impedance matching network which may be used. In a preferred embodiment, the invention is incorporated in a latteral diffused metal-oxide semiconductor (LDMOS) transistor to reduce hysteresis brought about by a drain bias circuit without any impact on the transistor output impedance By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced.

We claim:  
     
         1 . A radio frequency (RF) power transistor circuit comprising: 
 an RF power transistor with a gate/base, a drain/collector and a source/emitter;    an output matching network connected between the drain/collector and the source/emitter; and    means for applying a drain/collector biasing current to a low RF impedance point of the output matching network.    
     
     
         2 . The RF power transistor circuit of  claim 1  wherein the output matching network comprises an inductor in series with a capacitor, one end of the inductor connected to the drain/collector, one end of the capacitor connected to the source/emitter and a junction of the inductor and the capacitor serving as the low RF impedance point.  
     
     
         3 . The RF power transistor circuit of  claim 2  wherein the gate/base, the drain/collector, and the source/emitter are respectively connected to a first, second and third terminal on the RF power transistor circuit.  
     
     
         4 . The RF power transistor circuit of  claim 3  wherein the means for applying a drain/collector biasing current to a low RF impedance point of the output matching network comprises a fourth terminal on the RF power transistor circuit connected to the low RF impedance point.  
     
     
         5 . The RF power transistor circuit of  claim 4  wherein the RF power transistor is a field-effect transistor (FET).  
     
     
         6 . The RF power transistor circuit of  claim 5  wherein the FET is a laterally diffused metal-oxide semiconductor (LDMOS) FET.  
     
     
         7 . The RF power transistor circuit of  claim 4  wherein the RF power transistor is a bipolar junction transistor (RJT).  
     
     
         8 . A transistor package adapted to contain the RF power transistor circuit of  claim 4 .  
     
     
         9 . An RF power transistor circuit comprising: 
 an RF power transistor with a gate/base, a drain/collector and a source/emitter;    an output matching network connected between the drain/collector and the source/emitter wherein the output matching network comprises an inductor in series with a first capacitor, one end of the inductor connected to the drain/collector, one end of the first capacitor connected to the source/emitter;    means for applying a biasing current to the drain/collector; and    a second capacitor connected across the first capacitor and having a capacitance much greater than the capacitance of the first capacitor.    
     
     
         10 . The RF power transistor circuit of  claim 9  wherein the means for applying a biasing current to the drain/collector comprises a terminal on the RF power transistor circuit connected to the drain/collected gate/base.  
     
     
         11 . The RF power transistor circuit of  claim 10  wherein the RF power transistor is a FET.  
     
     
         12 . The RF power transistor circuit of  claim 10  wherein the RF power transistor is a BJT.  
     
     
         13 . An RF power transistor circuit comprising: 
 an RF power transistor with a gate/base, a drain/collector and a source/emitter;    an input matching network connected between the gate/base and the source/emitter; and    means for applying a gate/base biasing current to a low RF impedance point of the RF power transistor circuit.    
     
     
         14 . The RF power transistor circuit of  claim 13  wherein the low RF impedance point of the RF power transistor circuit is the gate/base.  
     
     
         15 . The RF power transistor circuit of  claim 14  wherein the means for applying a drain/collector biasing current to a low RF impedance point of the output matching network comprises a first terminal on the RF power transistor circuit connected to the gate/base.  
     
     
         16 . The RF power transistor circuit of  claim 15  wherein the drain/collector and the source/emitter are respectively connected to a second and third terminal on the RF power transistor circuit.  
     
     
         17 . The RF power transistor circuit of  claim 16  wherein the input matching network comprises a first and second inductors connected in series, one end of the first inductor connected to a fourth terminal of the RF power transistor circuit, one end of the second inductor connected to the gate/base, a junction of the first and second inductors connected to one end of a capacitor, the other end of which is connected to the source/emitter.  
     
     
         18 . The RF power transistor circuit of  claim 17  wherein the RF power transistor is a FET.  
     
     
         19 . The RF power transistor circuit of  claim 18  wherein the FET is an LDMOS FET.  
     
     
         20 . The RF power transistor circuit of  claim 17  wherein the RF power transistor is a BJT.  
     
     
         21 . A transistor package adapted to contain the RF power transistor circuit of  claim 17 .  
     
     
         22 . A method of biasing an RF power transistor in an RF power transistor circuit comprising: 
 generating a biasing current;    feeding the biasing current generated to a low RF impedance point in the RF power transistor circuit to bias the RF power transistor.    
     
     
         23 . The method of  claim 22  wherein generating a biasing current comprises generating a drain/collector biasing current.  
     
     
         24 . The method of  claim 23  wherein feeding the biasing current generated to a low RF impedance point in the RF power transistor circuit to bias the RF power transistor comprises feeding the biasing current generated through a dedicated terminal on the RF power transistor circuit connected to the low impedance point.  
     
     
         25 . The method of  claim 24  wherein feeding the biasing current generated to a low RF impedance point in the RF power transistor comprises feeding the drain/collector biasing current to a low RF impedance point in an output impedance matching network of the RF power transistor circuit.  
     
     
         26 . The method of  claim 22  wherein generating a biasing current comprises generating a gate/base biasing current.  
     
     
         27 . The method of  claim 26  wherein feeding the biasing current generated to a low RF impedance point in the RF power transistor comprises feeding the gate/base biasing current to a gate/base of the RF power transistor.  
     
     
         28 . The method of  claim 27  wherein feeding the biasing current generated to a low RF impedance point in the RF power transistor circuit to bias the RF power transistor comprises feeding the biasing current generated through a dedicated terminal on the RF power transistor circuit connected to the gate/base.  
     
     
         29 . The method of  claim 22  wherein feeding the biasing current generated to a low RF impedance point in the RF power transistor is done to reduce hysteresis in the RF power transistor.