Compact ISA-bus interface

Abstract

An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

What is claimed is:  
     
         1 . An interface structure, operable in at least a first mode of operation and a second mode of operation, for interfacing a host platform with a peripheral device, comprising: 
 an address-data bus coupled between said host platform and said peripheral device for carrying, in said first mode of operation, address information during an address phase of a first cycle and data information during a data phase of said first cycle, wherein said address information is multiplexed on said address-data bus with said data information such that said data phase follows said address phase in said first cycle; and    a device selected-backoff signal line coupled between said host platform and said peripheral device, for carrying a device selected signal asserted by said peripheral device indicating, in said first mode of operation, that said first cycle belongs to said peripheral device, and for carrying, in said second mode of operation, a backoff signal asserted by said peripheral device indicating whether said host platform should inhibit its access to said address-data bus.    
     
     
         2 . The interface structure of  claim 1 , further comprising: 
 a clock signal line coupled between said host platform and said peripheral device for carrying a clock signal;    an enable signal line coupled between said host platform and said peripheral device for carrying a signal at least indicating that said address information is valid in said first mode of operation;    a peripheral device ready signal line coupled between said host platform and said peripheral device for carrying a peripheral device ready signal indicating, in said first mode of operation, whether said peripheral device is ready to terminate said first cycle; and    a command signal line coupled between said host platform and said peripheral device for carrying, in said first mode of operation, a first timing signal indicating, in combination with at least said clock signal and said peripheral device ready signal, a time frame when a data transfer should take place in said data phase.    
     
     
         3 . The interface structure of  claim 2 , wherein: 
 said address-data bus carries, in said second mode of operation, interrupt request information during an interrupt request phase of a second cycle; and    said command signal line carries a second timing signal indicating, in said second mode of operation, during said interrupt request phase, in combination with said clock signal and said backoff signal, a time frame when said interrupt request information should be transferred.    
     
     
         4 . The interface structure of  claim 3 , wherein: 
 said address-data bus carries, in said second mode of operation, DMA request information during a DMA request phase of said second cycle, wherein said interrupt request information is multiplexed on said address-data bus with said DMA request information such that said DMA request phase follows said interrupt request phase in said second cycle; and    during said DMA request phase and after said interrupt request phase, said command signal line carries, in said second mode of operation, a signal indicating, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred.    
     
     
         5 . The interface structure of  claim 2 , wherein said second mode of operation is indicated by a signal on said enable signal line in combination with said clock signal, a signal on said device selected-backoff signal line and a signal on said command signal line.  
     
     
         6 . The interface structure of  claim 1 , wherein said address information includes an address which is in selectably a memory address space or an I/O address space, wherein said address-data bus includes an address space selection line for carrying a signal, in said first mode of operation during said first cycle and prior to said data phase, selecting one of said address spaces.  
     
     
         7 . The interface structure of  claim 1 , wherein said address information includes a cycle type which is selectably a memory access cycle, an I/O access cycle, a DMA acknowledge cycle, or a configuration cycle, wherein said address-data bus includes a cycle type line for carrying a signal, in said first mode of operation, during said first cycle and prior to said data phase, selecting one of said cycle types.  
     
     
         8 . The interface of  claim 7 , wherein: 
 said cycle type is a configuration cycle;    said host platform inhibits a clock signal to said peripheral device; and    said device selected-backoff signal line carries a signal indicating that said clock signal should be restarted.    
     
     
         9 . The interface structure of  claim 1 , wherein said address-data bus includes a direction indication line for carrying a signal, in said first mode of operation, during said first cycle and prior to said data phase, indicating a data transfer direction between said host platform and said peripheral device.  
     
     
         10 . The interface structure of  claim 1 , wherein said address information includes a cycle timing speed which is selectably fast timing or slow timing, wherein said address-data bus includes a timing selection indication line for carrying a signal, in said first mode of operation during said first cycle and prior to said data phase, for selecting one of said cycle timing speeds.  
     
     
         11 . The interface structure of  claim 1 , wherein said address information includes a first information part and a second information part, and said address phase includes a first address sub-phase and a second address sub-phase, wherein said address-data bus carries said first information part during said first address sub-phase and said second information part during said second address sub-phase, and wherein said first information part is multiplexed with said second information part on said address-data bus.  
     
     
         12 . The interface of  claim 1 , further comprising: 
 a speaker;    logic level holding means coupled to said speaker;    a speaker output line coupled between said host platform, said peripheral device and said logic level holding means, said speaker output line carrying a first speaker output signal of a first level; and    said logic level holding means maintaining said signal at said first level for at least a time period.    
     
     
         13 . The interface structure of  claim 2 , further comprising: 
 a reset signal line coupled between said host platform and said peripheral device for carrying a reset signal;    said enable signal line carrying a second signal indicating, in combination with said reset signal and said clock signal, a voltage threshold level.    
     
     
         14 . An interface structure for interfacing a host platform with a peripheral device, comprising: 
 a clock signal line coupled between said host platform and said peripheral device for carrying a clock signal;    a bus coupled between said host platform and said peripheral device,    said bus carries, in a first mode of operation, address information during an address phase of a first cycle and data information during a data phase of said first cycle, wherein said address information is multiplexed on said bus with said data information such that said data phase follows said address phase in said first cycle,    said bus carries, in a second mode of operation, interrupt request information during an interrupt request phase of a second cycle and DMA request information during a DMA request phase of said second cycle, wherein said interrupt request information is multiplexed on said bus with said DMA request information such that said DMA request phase follows said interrupt request phase in said second cycle, and    said bus including signal lines for carrying, in said first mode of operation, signals indicating a selected address space, a cycle type, a data transfer direction, and cycle timing;    an enable signal line coupled between said host platform and said peripheral device for carrying a signal at least indicating that said address information is valid in said first mode of operation;    a peripheral device ready signal line coupled between said host platform and said peripheral device for carrying a peripheral device reading signal indicating whether said peripheral device is ready to terminate said first cycle in said first mode of operation;    a device selected-backoff signal line coupled between said host platform and said peripheral device for carrying,    in said first mode of operation, a device selected signal indicating, in combination with a signal on said mode indication signal line, whether said first cycle belongs to said peripheral device, and    in said second mode of operation, a backoff signal indicating whether said host platform should inhibit access to said bus; and    a command signal line coupled between said host platform and said peripheral device for carrying a timing signal indicating a time frame when an information transfer should take place.    
     
     
         15 . The interface structure of  claim 14 , wherein said timing signal carried on said command signal line indicates when an information transfer should take place in combination with said clock signal and, 
 in said first mode of operation, said peripheral device ready signal; and    in said second mode of operation, said backoff signal.    
     
     
         16 . The interface structure of  claim 14 , wherein said selected address space includes one of a memory address space and an I/O address space.  
     
     
         17 . The interface structure of  claim 14 , wherein said cycle type includes one of an I/O cycle, a DMA acknowledge cycle, a memory cycle, and a configuration cycle.  
     
     
         18 . The interface of  claim 17 , wherein: 
 said cycle type is a configuration cycle;    said host platform cycle inhibits said clock signal to said peripheral device; and    said device selected-backoff signal line carries a signal indicating that said clock signal should be restarted.    
     
     
         19 . The interface structure of  claim 14 , wherein said data transfer direction includes one of a read direction and a write direction.  
     
     
         20 . The interface structure of  claim 14 , wherein said cycle timing includes one of fast timing and slow timing.  
     
     
         21 . The interface structure of  claim 14 , wherein said second mode of operation is indicated by a signal on said mode indication signal line in combination with said clock signal, a signal on said selected-backoff signal line and a signal on said command signal line.  
     
     
         22 . The interface structure of  claim 14 , wherein said address information includes a first information part and a second information part, and said address phase includes a first address sub-phase and a second address sub-phase, wherein said address-data bus carries said first information part during said first address sub-phase and said second information part during said second address sub-phase, and wherein said first information part is multiplexed with said second information part on said bus.  
     
     
         23 . The interface of  claim 14 , further comprising: 
 a speaker;    logic level holding means coupled to said speaker;    a speaker output line coupled between said host platform, said peripheral device and said logic level holding means, said speaker output line carrying a first speaker output signal of a first level; and    said logic level holding means maintaining said signal at said first level for at least a time period.    
     
     
         24 . The interface structure of  claim 14 , further comprising: 
 a reset signal line coupled between said host platform and said peripheral device for carrying a reset signal;    said enable signal line carrying a second signal indicating, in combination with said reset signal and said clock signal, a voltage threshold level.    
     
     
         25 . A host system for interfacing with a peripheral device through an interface in at least a first mode of operation and a second mode of operation, comprising: 
 a host platform circuit;    an address-data bus coupled between said host platform circuit and said interface, said address-data bus communicating, in said first mode of operation, address information provided by said host platform circuit during an address phase of a first cycle and communicating, in said first mode of operation, data information on said address-data bus during a data phase of said first cycle such that said address information is multiplexed with said data information on said address-data bus, said data phase following said address phase in said first cycle;    a device selected-backoff signal line coupled between said host platform circuit and said interface, said host platform circuit receiving a device selected signal from said device selected-backoff signal line indicating, in said first mode of operation, that said first cycle belongs to said peripheral device, and said host platform circuit receiving a backoff signal from said device selected-backoff signal line indicating, in said second mode of operation, whether said host platform should inhibit its access to said address-data bus.    
     
     
         26 . The host system of  claim 25 , further comprising: 
 a clock signal line coupled to said host platform circuit for carrying a clock signal;    an enable signal line coupled between said host platform circuit and said interface, said host platform circuit providing a signal to said enable signal line at least indicating, in said first mode of operation, that said address information is valid;    a peripheral device ready signal line coupled between said host platform circuit and said interface, said host platform circuit receiving a peripheral device ready signal from said peripheral device signal line indicating, in said first mode of operation, whether said peripheral device is ready to terminate said first cycle; and    a command signal line coupled between said host platform circuit and said interface, said host platform circuit providing a first timing signal to said command signal line indicating, in said first mode of operation, in combination with said clock signal and said peripheral device ready signal, a time frame when a data transfer should take place through said interface in said data phase.    
     
     
         27 . The host system of  claim 26 , wherein: 
 said address-data bus carries, in said second mode of operation, interrupt request information during an interrupt request phase of a second cycle; and    said command signal line carries a second timing signal indicating, in said second mode of operation, during said interrupt request phase, in combination with said clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface.    
     
     
         28 . The host system of  claim 27 , wherein: 
 said address-data bus carries, in said second mode of operation, DMA request information during a DMA request phase of said second cycle, wherein said interrupt request information is multiplexed on said address-data bus with said DMA request information such that said DMA request phase follows said interrupt request phase in said second cycle; and    during said DMA request phase and after said interrupt request phase, said command signal line carries, in said second mode of operation, a signal indicating, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         29 . The host system of  claim 26 , wherein said second mode of operation is indicated by a signal on said enable signal line in combination with said clock signal, a signal on said device selected-backoff signal line and a signal on said command signal line.  
     
     
         30 . The host system of  claim 25 , wherein said address information includes an address which is in selectably a memory address space or an I/O address space, wherein said address-data bus includes an address space selection line for carrying a signal provided by said host platform circuit, in said first mode of operation during said first cycle and prior to said data phase, selecting one of said address spaces.  
     
     
         31 . The host system of  claim 25 , wherein said address information includes a cycle type which is selectably a memory access cycle, an I/O access cycle, a DMA acknowledge cycle, or a configuration cycle, wherein said address-data bus includes a cycle type line for carrying a signal provided by said host platform circuit, in said first mode of operation during said first cycle and prior to said data phase, selecting one of said cycle types.  
     
     
         32 . The host system of  claim 31 , wherein: 
 said cycle type is a configuration cycle;    said host platform circuit inhibits a clock signal to said interface device; and    said device selected-backoff signal line carries a signal indicating that said clock signal should be restarted.    
     
     
         33 . The host system of  claim 25 , wherein said address-data bus includes a direction indication line for carrying a signal provided by said host platform circuit, in said first mode of operation, during said first cycle and prior to said data phase, indicating a data transfer direction between said host platform and said peripheral device.  
     
     
         34 . The host system of  claim 25 , wherein said address information includes a cycle timing speed which is selectably fast timing or slow timing, wherein said address-data bus includes a timing selection indication line for carrying a signal provided by said host platform circuit, in said first mode of operation, during said first cycle and prior to said data phase for selecting one of said cycle timing speeds.  
     
     
         35 . The host system of  claim 25 , wherein said address information includes a first information part and a second information part, and said address phase includes a first address sub-phase and a second address sub-phase, wherein said host platform circuit communicates said first information part through said address-data bus during said first address sub-phase and communicates said second information part through said address-data bus during said second address sub-phase, said first information part being multiplexed with said second information part on said address-data bus.  
     
     
         36 . The host system of  claim 25 , further comprising: 
 a speaker;    logic level holding means coupled to said speaker;    a speaker output line coupled between said host platform circuit, said interface and said logic level holding means, said speaker output line carrying a first speaker output signal of a first level; and    said logic level holding means maintaining said signal at said first level for at least a time period.    
     
     
         37 . The host system of  claim 26 , further comprising: 
 a reset signal line coupled between said host platform circuit and said interface for carrying a reset signal;    said enable signal line carrying a second signal indicating, in combination with said reset signal and said clock signal, a voltage threshold level.    
     
     
         38 . A peripheral system for interfacing with a host system through an interface in at least a first mode of operation and a second mode of operation, comprising: 
 a peripheral interface circuit;    an address-data bus coupled between said peripheral interface circuit and said interface, said address-data bus communicating, in said first mode of operation, address information received by said peripheral interface circuit during an address phase of a first cycle and communicating, in said first mode of operation, data information on said address-data bus during a data phase of said first cycle such that said address information is multiplexed with said data information on said address-data bus, said data phase following said address phase in said first cycle;    a device selected-backoff signal line coupled between said peripheral interface circuit and said interface, said peripheral interface circuit providing a device selected signal to said device selected signal line indicating, in said first mode of operation, that said first cycle belongs to said peripheral device; and    said peripheral interface circuit providing a backoff signal to said device selected-backoff signal line indicating, in said second mode of operation, whether said host system should inhibit its access to said address-data bus.    
     
     
         39 . The peripheral system of  claim 38 , further comprising: 
 a clock signal line for carrying a clock signal coupled to said peripheral interface circuit;    an enable signal line coupled between said peripheral interface circuit and said interface, said peripheral interface circuit receiving a signal from said enable signal line at least indicating, in said first mode of operation, that address information is valid;    a peripheral device ready signal line coupled between said peripheral interface circuit and said interface, said peripheral interface circuit providing a peripheral device ready signal to said peripheral device signal line indicating, in said first mode of operation, whether said peripheral device is ready to terminate said first cycle; and    a command signal line coupled between said peripheral interface circuit and said interface, said peripheral interface circuit receiving a first timing signal from said command signal line indicating, in said first mode of operation, in combination with said clock signal and said peripheral device ready signal, a time frame when a data transfer should take place in said data phase.    
     
     
         40 . The peripheral system of  claim 39 , wherein: 
 said address-data bus communicates, in said second mode of operation, interrupt request information during an interrupt request phase of a second cycle; and    said command signal line carries a second timing signal indicating, in said second mode of operation, during said interrupt request phase, in combination with said clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface.    
     
     
         41 . The peripheral system of  claim 40 , wherein: 
 said address-data bus communicating in said second mode of operation, DMA request information during a DMA request phase of said second cycle, wherein said interrupt request information is multiplexed on said address-data bus with said DMA request information such that said DMA request phase follows said interrupt request phase in said second cycle; and    during said DMA request phase and after said interrupt request phase, said command signal line carries, in said second mode of operation, a signal indicating, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         42 . The peripheral system of  claim 39 , wherein said second mode of operation is indicated by a signal on said enable signal line in combination with said clock signal, a signal on said device selected-backoff signal line and a signal on said command signal line.  
     
     
         43 . The peripheral system of  claim 38 , wherein said address information includes an address which is in selectably a memory address space or an I/O address space, wherein said address-data bus includes an address space selection line for carrying a signal received by said peripheral interface circuit, in said first mode of operation during said first cycle and prior to said data phase, selecting one of said address spaces.  
     
     
         44 . The peripheral system of  claim 38 , wherein said address information includes a cycle type which is selectably a memory access cycle, an I/O access cycle, a DMA acknowledge cycle, or a configuration cycle, wherein said address-data bus includes a cycle type line for carrying a signal received by said peripheral interface circuit, in said first mode of operation, during said first cycle and prior to said data phase, selecting one of said cycle types.  
     
     
         45 . The peripheral system of  claim 44 , wherein: 
 said cycle type is a configuration cycle;    said interface inhibits a clock signal to said peripheral device; and    said device selected-backoff signal line carries a signal indicating that said clock signal should be restarted.    
     
     
         46 . The peripheral system of  claim 38 , wherein said address-data bus includes a direction indication line for carrying a signal received by said peripheral interface circuit, in said first mode of operation, during said first cycle and prior to said data phase, indicating a data transfer direction between said host platform and said peripheral device.  
     
     
         47 . The peripheral system of  claim 38 , wherein said address information includes a cycle timing speed which is selectably fast timing or slow timing, wherein said address-data bus includes a timing selection indication line for carrying a signal received by said peripheral interface circuit, in said first mode of operation, during said first cycle and prior to said data phase for selecting one of said cycle timing speeds.  
     
     
         48 . The peripheral system of  claim 38 , wherein said address information includes a first information part and a second information part, and said address phase includes a first address sub-phase and a second address sub-phase, wherein said peripheral interface circuit receives said first information part through said address-data bus during said first address sub-phase and said second information part through said address-data bus during said second address sub-phase, said first information part being multiplexed with said second information part on said address-data bus.  
     
     
         49 . The peripheral system of  claim 38 , further comprising: 
 a speaker output line coupled between said peripheral interface circuit and said interface, said speaker output line carrying a first speaker output signal of a first level.    
     
     
         50 . The peripheral system of  claim 39 , further comprising: 
 a reset signal line coupled between said peripheral interface circuit and said interface for carrying a reset signal;    said enable signal line carrying a second signal indicating, in combination with said reset signal and said clock signal, a voltage threshold level.    
     
     
         51 . A method of interfacing a host system with a peripheral device through an interface, comprising the steps of: 
 communicating, in a first mode of operation, address information through an address-data bus to said interface in a first cycle;    communicating, in said first mode of operation, data information through said address-data bus such that said data information is multiplexed with said address information on said address-data bus in said first cycle;    receiving a device selected backoff-signal from said interface on a device selected-backoff signal line indicating that said first cycle belongs to said peripheral device; and    receiving a backoff signal from said interface on said device selected-backoff signal line indicating, in a second mode of operation, whether said host system should inhibit its access to said address-data bus.    
     
     
         52 . The method of  claim 51 , further comprising the steps of: 
 sending an enable signal to said interface on an enable signal line at least indicating, in said first mode of operation, that said address information is valid;    receiving a peripheral device ready signal from said interface indicating, in said first mode of operation, whether said peripheral device is ready to terminate said first cycle; and    sending a first command signal on a command signal line to said interface indicating, in said first mode of operation, in combination with a clock signal and said peripheral device ready signal, a time frame when a data transfer should take place through said interface.    
     
     
         53 . The method of  claim 52 , further comprising the step of: 
 communicating, in said second mode of operation, interrupt request information through said address-data bus in a second cycle; and    sending a second command signal on said command signal line to said interface indicating, in said second mode of operation, in combination with said clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface.    
     
     
         54 . The method of  claim 53 , further comprising: 
 communicating, in said second mode of operation and after said step of communicating said interrupt request information, DMA request information through said address-data bus, wherein said DMA request information is multiplexed with said interrupt request information such that said interrupt request information precedes said DMA request information; and    sending a third command signal on said command signal line to said interface indicating, in said second mode of operation, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         55 . The method of  claim 52 , wherein said second mode of operation is indicated by the step of sampling inactive signals on said device selected-backoff signal line, said command signal line, and said enable signal line for a specified time period.  
     
     
         56 . The method of  claim 51 , wherein: 
 said step of communicating said address information includes driving said address information onto the address-data bus; and    said step of communicating said data information includes receiving said data information from the address-data bus.    
     
     
         57 . The method of  claim 51 , wherein said address information includes an address which is in selectably a memory address space or an I/O address space, and wherein said step of communicating said address information includes communicating an address space selection signal, in said first mode of operation during said first cycle, selecting one of said address spaces.  
     
     
         58 . The method of  claim 51 , wherein said address information includes a cycle type which is selectably a memory access cycle, an I/O access cycle, a DMA acknowledge cycle, or a configuration cycle, and wherein said step of communicating address information includes communicating a cycle type signal, in said first mode of operation, during said first cycle, selecting one of said cycle types.  
     
     
         59 . The method of  claim 58  wherein said cycle type is a configuration cycle, further comprising the steps of: 
 inhibiting said clock signal to said interface; and  
 receiving a clock run signal from said device selected-backoff signal line indicating that said clock signal should be restarted.  
 
     
     
         60 . The method of  claim 51 , wherein said step of communicating address information includes communicating a direction indication signal, in said first mode of operation during said first cycle, indicating a data transfer direction between said interface and said peripheral device.  
     
     
         61 . The method of  claim 51 , wherein said address information includes a cycle timing speed which is selectably fast timing or slow timing, wherein said step of communicating address information includes communicating a timing selection indication signal, in said first mode of operation during said first cycle, for selecting one of said cycle timing speeds.  
     
     
         62 . The method of  claim 51 , wherein said address information includes a first information part and a second information part, and wherein said step of communicating said address information includes the step of multiplexing said first information part with said second information part on said address-data bus.  
     
     
         63 . The method of  claim 51 , further comprising the steps of: 
 sampling a source input signal of a first logic level on a source input signal line;    sampling a speaker output signal of a second logic level on a speaker output line;    resampling said source input signal; and    driving said speaker output signal to a third logic level if said source input signal is a fourth logic level.    
     
     
         64 . The method of  claim 51 , further comprising the steps of: 
 communicating a reset signal through said interface;    communicating an enable signal through said interface indicating, in combination with a clock signal and said reset signal, a voltage threshold level.    
     
     
         65 . A method of interfacing a host system with a peripheral device through an interface, comprising the steps of: 
 communicating interrupt request information through a bus in a cycle;    receiving a backoff signal from said interface indicating whether said host system should inhibit its access to said bus;    sending a first command signal on a command signal line to said interface indicating, in combination with a clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface;    communicating DMA request information through said bus, such that said DMA request information is multiplexed with said interrupt request information; and    sending a second command signal on said command signal line to said interface indicating, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         66 . A method of interfacing a peripheral device with a host system through an interface, comprising the steps of: 
 communicating, in a first mode of operation, address information through an address-data bus in a first cycle;    communicating, in said first mode of operation, data information through said address-data bus such that said data information is multiplexed with said address information on said address-data bus in said first cycle;    sending a device selected signal on a device selected-backoff signal line to said interface indicating that said first cycle belongs to said peripheral device; and    sending a backoff signal on said device selected-backoff signal line to said interface indicating, in a second mode of operation, whether said host system should inhibit its access to said address-data bus.    
     
     
         67 . The method of  claim 66 , further comprising the step of: 
 receiving an enable signal from said interface on an enable signal line at least indicating, in said first mode of operation, that said address information is valid;    sending a peripheral device ready signal to said interface indicating, in said first mode of operation, whether said peripheral device is ready to terminate said first cycle; and    receiving a first command signal on a command signal line from said interface indicating, in said first mode of operation, in combination with a clock signal and said peripheral device ready signal, a time frame when a data transfer should take place through said interface.    
     
     
         68 . The method of  claim 67 , further comprising the steps of: 
 communicating, in a second mode of operation, interrupt request information through said address-data bus in said second cycle; and    receiving a second command signal on said command signal line from said interface indicating, in said second mode of operation, in combination with said clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface.    
     
     
         69 . The method of  claim 68 , further comprising: 
 communicating, in said second mode of operation and after said step of communicating said interrupt request information, DMA request information through said address-data bus, wherein said DMA request information is multiplexed with said interrupt request information such that said interrupt request information precedes said DMA request information; and    receiving a third command signal on said command signal line from said interface indicating, in said second mode of operation, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         70 . The method of  claim 67 , wherein said second mode of operation is indicated by the step of sampling inactive signals on said device selected-backoff signal line, said command signal line, and said enable signal line for a specified time period.  
     
     
         71 . The method of  claim 66 , wherein: 
 said step of communicating said address information includes receiving said address information from the address-data bus; and    said step of communicating said data information includes sending said data information through the address-data bus.    
     
     
         72 . The method of  claim 66 , wherein said address information includes an address which is in selectably a memory address space or an I/O address space and wherein said step of communicating said address information includes communicating an address space selection signal, in said first mode of operation during said first cycle, selecting one of said address spaces.  
     
     
         73 . The method of  claim 66 , wherein said address information includes a cycle type which is selectably a memory access cycle, an I/O access cycle, a DMA acknowledge cycle, or a configuration cycle and wherein said step of communicating address information includes communicating a cycle type signal, in said first mode of operation during said first cycle, selecting one of said cycle types.  
     
     
         74 . The method of  claim 73 , wherein said cycle type is a configuration cycle and a clock signal is received on a clock signal line, further comprising the steps of: 
 receiving a steady signal on said clock signal line from said interface indicating said clock signal has been stopped; and    sending a clock run signal on said device selected-backoff signal line to said interface indicating that said clock signal should be restarted.    
     
     
         75 . The method of  claim 66 , wherein said step of communicating address information includes communicating a direction indication signal, in said first mode of operation during said first cycle, indicating a data transfer direction between said host platform and said peripheral device.  
     
     
         76 . The method of  claim 66 , wherein said address information includes a cycle timing speed which is selectably fast timing or slow timing, wherein said step of communicating address information includes communicating a timing selection indication signal, in said first mode of operation during said first cycle, for selecting one of said cycle timing speeds.  
     
     
         77 . The method of  claim 66 , wherein said address information includes a first information part and a second information part, and wherein said step of communicating said address information includes the step of multiplexing said first information part with said second information part on said address-data bus.  
     
     
         78 . The method of  claim 66 , further comprising the steps of: 
 sampling a source input signal of a first logic level on a source input signal line;    sampling a speaker output signal of a second logic level on a speaker output line;    resampling said source input signal; and    driving said speaker output signal to a third logic level if said source input signal is a fourth logic level.    
     
     
         79 . The method of  claim 66 , further comprising the steps of: 
 communicating a reset signal through said interface;    communicating an enable signal through said interface indicating, in combination with a clock signal and said reset signal, a voltage threshold level.    
     
     
         80 . A method of interfacing a peripheral device with a host system through an interface, comprising the steps of: 
 communicating interrupt request information through a bus in a cycle;    sending a backoff signal to said interface indicating whether said host system should inhibit its access to said bus;    receiving a first command signal on a command signal line from said interface indicating, in combination with a clock signal and said backoff signal, a time frame when said interrupt request information should be transferred through said interface;    communicating DMA request information through said bus, such that said DMA request information is multiplexed with said interrupt request information; and    receiving a second command signal on said command signal line from said interface indicating, in combination with said clock signal and said backoff signal, a time frame when said DMA request information should be transferred through said interface.    
     
     
         81 . Apparatus for interfacing a first device and a second device with a speaker, comprising: 
 logic level holding means coupled to said speaker;    a speaker output line coupled between said first device, said second device and said logic level holding means, said speaker output line carrying a first speaker output signal of a first level; and    said logic level holding means maintaining said signal at said first level for at least a time period.    
     
     
         82 . The apparatus of  claim 81 , wherein said logic level holding means is a capacitive logic level holding means.  
     
     
         83 . The apparatus of  claim 82 , wherein said capacitive logic level holding means is bus capacitance.  
     
     
         84 . The apparatus of  claim 82 , wherein said capacitive logic level holding means is a capacitor.  
     
     
         85 . The apparatus of  claim 81  wherein a second speaker output signal is carried on said speaker output line at a time after said first speaker output signal is carried on said speaker output line and wherein said time period is said time.  
     
     
         86 . A method of interfacing a first device and a second device with a speaker, comprising the steps of: 
 sampling a source input signal of a first logic level on a source input signal line;    sampling a speaker output signal of a second logic level on a speaker output line coupled between said first device and said second device;    resampling said source input signal; and    driving said speaker output signal to a third logic level if said source input signal is a fourth logic level.    
     
     
         87 . The method of  claim 86  wherein: 
 said first logic level and said second logic level are equivalent; and  
 said third logic level and said fourth logic level are equivalent.  
 
     
     
         88 . The method of  claim 86  wherein: 
 said first logic level and said third logic level are equivalent; and  
 said second logic level and said fourth logic level are equivalent.  
 
     
     
         89 . The method of  claim 86 , wherein: 
 said first logic level and said fourth logic level are equivalent; and    said second and said third logic level are equivalent.    
     
     
         90 . The method of  claim 86 , further comprising the step of: 
 holding said speaker output signal to said third logic level for at least a specified time.    
     
     
         91 . A method of interfacing a first device and a second device with a speaker, comprising the steps of: 
 asserting a speaker output signal of a first logic level on a speaker output signal line shared between said first device and said second device;    toggling, by said first device, said speaker output signal to a second logic level;    toggling, by said second device, said speaker output signal to said first logic level.    
     
     
         92 . The method of claim  91 , wherein said first logic level is a logical high and said second logic level is a logical low.  
     
     
         93 . A system for interfacing a first device with a second device through an interface, comprising: 
 a clock signal line coupled between said first device and said interface for carrying a clock signal;    a reset signal line coupled between said first device and said interface for carrying a reset signal;    an enable signal line coupled between said first device and said interface for carrying a signal indicating, in combination with said reset signal and said clock signal, a voltage threshold level.    
     
     
         94 . The host system of claim  93 , wherein said voltage threshold level is approximately 3.3 volts.  
     
     
         95 . The host system of claim  93 , wherein said voltage threshold level is approximately 5 volts.  
     
     
         96 . A method of interfacing a host system with a peripheral device through an interface, comprising the steps of: 
 communicating a reset signal through said interface;    communicating an enable signal through said interface indicating, in combination with a clock signal and said reset signal, a voltage threshold level.    
     
     
         97 . The method of interfacing of claim  96 , wherein said step of communicating an enable signal indicates a voltage threshold level of approximately 3.3 volts.