Semiconductor integrated circuit and recording medium

Abstract

Disclosed herein are a semiconductor integrated circuit and a recording medium wherein the amount of test data inputted from and outputted to the outside to test a plurality of circuit modules and the amount of test result data are reduced and a test time interval is shortened. When each of tested circuits is tested, test control information is externally inputted to a test interface circuit, and test control information is set to each of scan registers of circuit modules to be tested, through a test signal chain. When an instruction for a test operation is given to each of test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Test results are read into the test interface circuit from the scan registers through the test signal chain, followed by output to the outside. The test operations for the circuit modules can be parallelized and the test interface circuit can be shared between the respective circuit modules.

What is claimed is:  
     
         1 . A semiconductor integrated circuit, comprising: 
 a single semiconductor chip including, 
 a plurality of circuit modules each provided with a test input terminal, a test output terminal and a test control terminal;  
 a test path which connects the test output terminal of one circuit module to the test input terminal of the other circuit module to thereby form a test signal chain; and  
 a test interface circuit connected to the test path; and  
   wherein said each circuit module has a tested circuit, a test register circuit and a test control circuit,    said test register circuit is connected to the test path through the test input terminal and the test output terminal and permits input and output to and from the test control circuit;    said test control circuit receives a start for a test on said each tested circuit from the test control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit; and    said test interface circuit supplies the test control information to the test register circuit from the outside through the test path and outputs the information about the result of test from the test register circuit to the outside through the test path.    
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein said test control circuit has a test pattern generator and a compressor, and said test pattern generator generates a test pattern for said each tested circuit, based on the test control information inputted to the test register circuit and said compressor compresses the result of operation of the tested circuit to thereby generate information about the result of test and supplies the same to the test register circuit.  
     
     
         3 . The semiconductor integrated circuit according to  claim 1  or  2 , wherein the control terminals of said plurality of circuit modules are connected in common and coupled to the test interface circuit.  
     
     
         4 . The semiconductor integrated circuit according to any of  claims 1  to  3 , wherein said test path series-connects the plurality of test register circuits with the test interface circuit as a base point and constitutes a scan path fed back to the test interface circuit.  
     
     
         5 . The semiconductor integrated circuit according to  claim 2 , wherein said test register circuit is a plural-bits type shift register having a serial input terminal connected to the test input terminal, a serial output terminal connected to the test output terminal, a parallel output terminal connected to the pattern generator, and a parallel input terminal connected to the compressor.  
     
     
         6 . The semiconductor integrated circuit according to  claim 4  or  5 , wherein said test path includes paths provided in plural form, which connect the test register circuits in series.  
     
     
         7 . The semiconductor integrated circuit as claim in  claim 1  or  2 , wherein said test control information is a test command for giving instructions for the contents of each test operation.  
     
     
         8 . The semiconductor integrated circuit according to any of  claims 1  to  7 , wherein one of said plurality of circuit modules is a cache memory.  
     
     
         9 . The semiconductor integrated circuit according to any of  claims 1  to  7 , wherein one of said plurality of circuit modules is a dynamic random access memory.  
     
     
         10 . The semiconductor integrated circuit according to any of  claims 1  to  7 , wherein said plurality of circuit modules include a first circuit module connected to a common bus, and a second circuit module connected to the first circuit module and disconnected from the common bus.  
     
     
         11 . The semiconductor integrated circuit according to  claim 10 , wherein said second circuit module is a local memory.  
     
     
         12 . The semiconductor integrated circuit according to any of  claims 4  to  6 , wherein said test interface circuit has a clock terminal, a mode terminal, a data input terminal and a data output terminal as external terminals, and when a first operation mode is specified through the mode terminal, said test interface circuit captures information supplied to the data input terminal and delivers the captured information to the test path, when a second operation mode is specified through the mode terminal, said test interface circuit captures information supplied to the data input terminal and decodes the captured information to thereby output a control signal to the test control terminal, and when a third operation mode is specified through the mode terminal, said test interface circuit captures information in each test register circuit through the test path and outputs the same from the data output terminal to the outside.  
     
     
         13 . The semiconductor integrated circuit according to  claim 12 , wherein said test interface circuit performs the input/output of a signal in accordance with a procedure which complies with the standard of IEEE1149.1.  
     
     
         14 . A storage medium having circuit module data used for designing an integrated circuit to be formed on a semiconductor chip by using a computer, said circuit module data being stored therein so as to be readable by the computer, said circuit module data including, 
 graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test input terminal, a test output terminal, a test control terminal, a normal interface terminal, a tested circuit connected to the normal interface terminal, a test register circuit for inputting information from the test input terminal and outputting the information to the test output terminal, and a test control circuit for receiving a start for a test on the tested circuit from the control terminal to thereby perform the test using test control information outputted from the test register circuit and supplying information about the result of test to the test register circuit.    
     
     
         15 . The storage medium according to  claim 14 , wherein said test control circuit has a test pattern generator and a compressor, and said test pattern generator generates a test pattern for said each tested circuit, based on the test control information inputted to the test register circuit and said compressor compresses the result of operation of the tested circuit to thereby generate information about the result of test and supplies the same to the test register circuit.  
     
     
         16 . The storage medium according to  claim 15 , wherein said test register circuit is a plural-bits type shift register having a serial input terminal connected to the test input terminal, a serial output terminal connected to the test output terminal, a parallel output terminal connected to the pattern generator, and a parallel input terminal connected to the compressor.  
     
     
         17 . The storage medium according to  claim 16 , wherein said circuit module is a cache memory.  
     
     
         18 . The storage medium according to  claim 16 , wherein said circuit module is a dynamic random access memory.  
     
     
         19 . A storage medium having: 
 circuit module data according to  claim 14 , which are respectively provided for a plurality of circuit modules different in tested circuit from one another, and    test path data used as graphics pattern data or function descriptive data for forming, on a semiconductor chip with the plurality of circuit modules formed thereon, a test path for connecting a test output terminal of one circuit module to a test input terminal of another circuit module to thereby constitute a test signal chain, said test path data being computer-readably provided for the respective circuit modules.    
     
     
         20 . The storage medium according to  claim 19 , further including test interface circuit information defined as graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test interface circuit which supplies the test control information from the outside to the test register circuit through the test path and outputs information about the result of test from the test register circuit to the outside through the test path.  
     
     
         21 . A storage medium having: 
 circuit module data for designing an integrated circuit to be formed on a semiconductor chip by using a computer, said circuit module data being stored therein so as to be readable by the computer, said circuit module data including, 
 graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test input terminal, a test output terminal, a test control terminal, a normal interface terminal connected to each tested circuit, a test register circuit which inputs information from the test input terminal and outputs the information to the test output terminal, and a test control circuit which receives a start for a test on the tested circuit from the control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit.  
   
     
     
         22 . Circuit module data for designing an integrated circuit to be formed on a semiconductor chip by using a computer, said circuit module data including: 
 graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test input terminal, a test output terminal, a test control terminal, a normal interface terminal, a tested circuit connected to the normal interface terminal, a test register circuit which inputs information from the test input terminal and outputs the information to the test output terminal, and a test control circuit which receives a start for a test on the tested circuit from the control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit.    
     
     
         23 . Circuit module data for designing an integrated circuit to be formed on a semiconductor chip by using a computer, said circuit module data including: 
 graphics pattern data or function descriptive data for forming, on the semiconductor chip, a test input terminal, a test output terminal, a test control terminal, a normal interface terminal connected to each tested circuit, a test register circuit which inputs information from the test input terminal and outputs the information to the test output terminal, and a test control circuit which receives a start for a test on the tested circuit from the control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit.