Metal oxide semiconductor transistor with self-aligned channel implant

Abstract

A transistor ( 50 ) comprising a gate conductor ( 68 ) and a gate insulator ( 66 ) separating the gate conductor from a semiconductor material ( 64 ) having a first conductivity type. The transistor further comprises a drain region ( 72 2 ) having the first conductivity type. The transistor further comprises an angular implanted region ( 70 ) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge ( 70 a ) underlying the gate conductor, and the transistor includes a source region ( 72 1 ) formed at least in part within the angular implanted region. Finally, a transistor channel ( 74 ) is defined between an edge ( 72 a 1 ) of the source region proximate the gate conductor and the angular implanted region edge ( 70 a ) underlying the gate conductor.

1 . A transistor, comprising: 
 a gate conductor;    a gate insulator separating the gate conductor from a semiconductor material having a first conductivity type;    a drain region having the first conductivity type;    an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor;    a source region formed within the angular implanted region; and    a transistor channel defined between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor:    
     
     
         2 . The transistor of  claim 1  wherein the edge of the source region proximate the gate conductor is self-aligned with respect to the gate conductor.  
     
     
         3 . The transistor of  claim 2  wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.  
     
     
         4 . The transistor of  claim 3  wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.  
     
     
         5 . The transistor of claim  4 : 
 and further comprising a p-type semiconductor substrate;    and wherein the semiconductor material comprises an n-well formed in the p-type semiconductor substrate.    
     
     
         6 . The transistor of  claim 5  and further comprising: 
 a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and  
 an insulating region proximate one edge of the gate conductor;  
 and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.  
 
     
     
         7 . The transistor of  claim 6  wherein the drain region has a higher dopant concentration than the semiconductor material.  
     
     
         8 . The transistor of  claim 7  wherein the source region has the first conductivity type.  
     
     
         9 . The transistor of  claim 1  wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.  
     
     
         10 . The transistor of  claim 1  wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.  
     
     
         11 . The transistor of  claim 1:   and further comprising a p-type semiconductor substrate;    and wherein the semiconductor material comprises an n-well formed in the p-type semiconductor substrate.    
     
     
         12 . The transistor of  claim 1  and further comprising: 
 a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and  
 an insulating region proximate one edge of the gate conductor;  
 and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.  
 
     
     
         13 . The transistor of  claim 1  wherein the drain region has a higher dopant concentration than the semiconductor material.  
     
     
         14 . The transistor of  claim 1  wherein the source region has the first conductivity type.  
     
     
         15 . A method of forming an integrated circuit, comprising the steps of: 
 forming a gate insulator;    forming a gate conductor relative to the gate insulator such that the gate insulator separates the gate conductor from a semiconductor material having a first conductivity type;    forming a drain region having the first conductivity type;    performing an angular implant to form an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor;    forming a source region formed within the angular implanted region; and    wherein the steps of performing an angular implant and forming a source region define a transistor channel between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor.    
     
     
         16 . The method of claim  15 : 
 wherein the gate insulator, the gate conductor, the source region, the drain region, and the angular implanted region form a first transistor;    and further comprising forming a second transistor comprising the step of using the angular implant to form at least one region of the second transistor into a previously-formed region of the second transistor.    
     
     
         17 . The method of  claim 16  wherein the at least one region has a conductivity type which is the same as a conductivity type of the previously-formed region.  
     
     
         18 . The method of  claim 15  wherein the edge of the source region proximate the gate conductor is self-aligned with respect to the gate conductor.  
     
     
         19 . The method of  claim 18  wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.  
     
     
         20 . The method of  claim 19  wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.  
     
     
         21 . The method of  claim 20  wherein the semiconductor material comprises an n-well formed in a p-type semiconductor substrate.  
     
     
         22 . The method of  claim 21  and further comprising: 
 forming a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and  
 forming an insulating region proximate one edge of the gate conductor;  
 and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.  
 
     
     
         23 . The method of  claim 22  wherein the drain region has a higher dopant concentration than the semiconductor material.