Field effect transistor

Abstract

An FET (Field Effect Transistor) has an epitaxial wafer including an Al 0.2 Ga 0.8 As gate contact layer. A GaAs gate buried layer doped with Si, Al 0.2 Ga 0.8 As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 Ω·mm is achievable which is lower than the conventional ON resistance by 0.2 Ω·mm.

What is claimed is:  
     
         1 . In an FET (Field Effect Transistor) using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         2 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         3 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a first AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         4 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said second GaAs layer, and said second GaAs gate buried layer and a gate electrode contact with each other without any gap.  
     
     
         5 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes undoped layers respectively contacting said first and third AlGaAs layers, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         6 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity or an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         7 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity or an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth AlGaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         8 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         9 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         10 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         11 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.  
     
     
         12 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.  
     
     
         13 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.  
     
     
         14 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes undoped layers respectively contacting said first and third AlGaAs layers, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.  
     
     
         15 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity and an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.  
     
     
         16 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity and an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.  
     
     
         17 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.  
     
     
         18 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.  
     
     
         19 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         20 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of a layer doped with an n-type impurity, a layer doped with a high concentration n-type impurity and an n-type doped layer, as named from a side contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.  
     
     
         21 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, and said GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.  
     
     
         22 . In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three layer structure made up of a layer doped with an n-type impurity, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.