Method of fabricating semiconductor device

Abstract

The object of the present invention is to provide a semiconductor device having small mounting area with reduced cost. A board with a plurality of device carrier areas thereon and an electrode pattern serving as external electrodes on a back of the board is prepared, and semiconductor chips are fixed respectively to the device carrier areas. The semiconductor chips fixed to the device carrier areas are covered with a common resin layer. A round surface of the common resin layer is flattened into a flat and horizontal surface, and a dicing sheet is applied to the flat and horizontal surface of the common resin layer with the electrode pattern facing upwardly. The board and the common resin layer are separated into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from the back of the board.

What is claimed is:  
     
         1 . A method of fabricating a semiconductor device, comprising the steps of: 
 preparing a board with a plurality of device carrier areas thereon;    fixing semiconductor chips respectively to said device carrier areas;    covering said semiconductor chips fixed to said device carrier areas with a common resin layer;    flattening a surface of said common resin layer;    applying a dicing sheet to the flattened surface of said common resin layer; and    separating said board and said common resin layer into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from a back of said board.    
     
     
         2 . A method according to  claim 1 , further comprising the step of: 
 placing an electrode pattern serving as external electrodes of the semiconductor chips on said back of said board, said electrode pattern being spaced inwardly from dicing lines along edges of said segments so as to be kept out of contact with a dicing blade along said dicing lines.    
     
     
         3 . A method according to  claim 1 , wherein an electrically conductive pattern is formed on a surface of said board for fixing said semiconductor chip, and another electrically conductive pattern is formed for external connection at back of said board which connects to said conductive pattern via through hole filled with conductive material.  
     
     
         4 . A method according to  claim 1 , wherein said board comprises of ceramics or glass epoxy.  
     
     
         5 . A method according to  claim 1 , wherein said resin layer comprises of epoxy resin.