Cmos process

Abstract

A high-voltage MOS transistor is produced in a low-voltage CMOS process without adding extra process steps for producing the high-voltage MOS transistor. The high-voltage MOS transistor is to be used as an analog line driver and is produced on the same silicon area as low voltage AD/DA- converters. Hereby, the low-voltage and the high-voltage design block are directly compatible with each other, e.g. have the same threshold voltages, which simplifies the design of the total solution.

1 . A method of producing, in a CMOS process, a high-voltage MOS transistor together with a low-voltage NMOS transistor and a low-voltage PMOS transistor on a substrate, comprising 
 producing a mask on the substrate with openings defining where n-well regions are to be located in the substrate for the high-voltage MOS transistor and the low-voltage PMOS transistor,    doping the substrate through said mask openings to produce the n-well regions for both the high-voltage MOS transistor and the low-voltage PMOS transistor in the same process step,    removing the mask,    depositing a protective film on the substrate,    removing the protective film except where source, gate and drain regions for both the high-voltage MOS transistor and the low-voltage NMOS and PMOS transistors are to be located,    exposing the substrate to an oxidizing atmosphere to produce an oxide on areas not covered by the protective film,    removing the rest of the protective film,    defining the gate regions for both the high-voltage MOS transistor and the low-voltage NMOS and PMOS transistors by producing a thin gate oxide on the substrate, depositing a layer of poly-Si thereon, and patterning the poly-Si layer,    defining n + -regions corresponding to the drain and source regions for the low-voltage NMOS transistor and for the high-voltage MOS transistor in the same process step.    
     
     
         2 . The method as claimed in  claim 1 , characterized in that the poly-Si patterned as a gate for the high-voltage MOS transistor, extends over the oxide edge, whereby the thickness of the oxide under the gate of the high-voltage MOS transistor differs towards the source and the drain, respectively.  
     
     
         3 . The method as claimed in  claim 2 , characterized in that the difference between the thickness of the oxide under the gate on the source side and on the drain side, is selected to be larger than a factor 10.  
     
     
         4 . The method as claimed in  claim 1 , characterized in that the channel length of the high-voltage MOS transistor is determined by the fitting between the mask for defining the n-well regions and the gate poly-Si.  
     
     
         5 . The method as claimed in  claim 1 , characterized in that the high-voltage MOS transistor can withstand voltages twice as high as the low-voltage transistors.  
     
     
         6 . The method as claimed in  claim 1 , characterized in that the threshold voltage of the low-voltage NMOS transistor and the high-voltage MOS transistor is the same.  
     
     
         7 . The method as claimed in  claim 1 , characterized in that the substrate is selected to be a p-type substrate.  
     
     
         8 . The method as claimed in  claim 1 , characterized in that the substrate is selected to comprise is a p-type silicon layer on a differently doped substrate.  
     
     
         9 . Use of a high-voltage MOS transistor, produced on a substrate in the same process as low-voltage CMOS transistors, as an analog line driver at the same time as the low-voltage CMOS transistors are used as AD/DA converters.