Semiconductor device having MISFETs

Abstract

A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.

1 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage;    performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate;    forming a first film covering the first and second gate electrodes, above the semiconductor substrate;    performing anisotropic etching on the first film, thereby forming a first side-all film on sides of the first and second gate electrodes;    performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET in the semiconductor substrate;    forming a second film covering the first and second gate electrode, above the semiconductor substrate;    performing anisotropic etching on the second film, thereby forming a second side-all film on sides of the first and second gate electrodes; and    performing ion implantation, thereby forming a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.    
     
     
         2 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage;    performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate;    forming a first film covering the first and second gate electrodes, above the semiconductor substrate;    forming a second film on the first film, said second film being different in material from the first film;    performing anisotropic etching on the second film, thereby forming a first side-all film at a stepped part near the first gate electrode and a stepped part near the second gate electrode; and    performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET, in the semiconductor substrate.    
     
     
         3 . A method of manufacturing a semiconductor device, comprising the steps of: 
 forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage;    performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate;    forming a first film covering the first and second gate electrodes, above the semiconductor substrate;    forming a second film on the first film, said second film being different in material from the first film;    performing partial etching on the second film, thereby removing a part of the second film which lies above the first MISFET and leaving the second film above the second MISFET;    performing anisotropic etching on the second film, thereby forming a first side-wall film at a stepped part near the second gate electrode;    performing anisotropic etching on the first film, thereby forming a second side-all film on sides of the first and second gate electrodes; and    performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.