Double-bit non-voltatile memory unit and corresponding data read/write method

Abstract

A double-bit non-volatile memory cell structure and a method of programming the memory cell. The memory cell includes a pair of stacked gates above a substrate, a doped region in the substrate between the stacked gate pair and a source/drain region in the substrate on each side of the stacked gate pair. The source/drain regions and the doped region are doped identically. To write data into the memory cell, the channel underneath both stacked gates is opened simultaneously. Data is written into the desired floating gate by controlling current flow direction. To read data from a first floating gate of the memory cell, a read bias voltage is applied to the first control gate above the first floating gate. In the meantime, a transfer voltage is applied to the second control gate. The presence or the absence of a conductive channel between the source/drain regions indicates whether data has been written into the first floating gate or not. The read bias voltage is greater than the threshold voltage of the first/the second floating gate in the erased state but smaller than the threshold voltage in the written state. The transfer voltage is greater than the threshold voltage in the written state.

What is claimed is:  
     
         1 . A double-bit non-volatile memory cell structure, comprising: 
 a substrate;    a pair of stacked gates above the substrate, wherein each stacked gate includes, from bottom to top, a tunnel layer, a floating gate, an inter-gate dielectric layer and a control gate;    a doped region, wherein the doped region is located in the substrate between the two stacked gates; and    a pair of source/drain regions, wherein the source/drain regions are in the substrate on each side of the stacked gate pair, and the two source/drain regions and the doped region are identically doped.    
     
     
         2 . The structure of  claim 1 , wherein the double-bit non-volatile memory cell is applied to form a flash memory.  
     
     
         3 . The structure of  claim 1 , wherein the tunnel layer includes a tunnel oxide layer.  
     
     
         4 . The structure of  claim 1 , wherein material forming the floating gate includes polysilicon.  
     
     
         5 . The structure of  claim 1 , wherein the inter-gate dielectric layer includes an oxide/nitride/oxide (ONO) composite layer.  
     
     
         6 . The structure of  claim 1 , wherein the material forming the control gate includes polysilicon.  
     
     
         7 . The structure of  claim 1 , wherein the width of the doped region is smaller than the width of any one of the pair of source/drain regions.  
     
     
         8 . The structure of  claim 1 , wherein the doped region has a width identical to any one of the pair of source/drain regions.  
     
     
         9 . The structure of  claim 1 , wherein the doped region and the two source/drain regions are all n-doped.  
     
     
         10 . A method of programming a double-bit non-volatile memory cell, wherein the double-bit non-volatile memory cell comprises: 
 a substrate;    a first stacked gate and a second stacked gate above the substrate, wherein the first stacked gate includes a first floating gate and a first control gate and the second stacked gate includes a second floating gate and a second control gate;    a doped region located in the substrate between the first stacked gate and the second stacked gate; and    a pair of source/drain regions located in the substrate on each side of the stacked gate pair, wherein the two source/drain regions and the doped region are n-doped; and    the steps of writing data into the first floating gate includes:    applying a first voltage at the first control gate and applying a second voltage at the second control gate so that the channel underneath the first floating gate and the channel underneath the second floating gate are both opened; and    applying a different bias voltage at the two source/drain regions so that electrons in the channel underneath the second floating gate flow towards the channel underneath the first floating gate, and the electrons pick up sufficient energy from the channel underneath the first floating gate to produce hot electrons that can easily move into the first floating gate.    
     
     
         11 . The programming method of  claim 10 , wherein after the step of writing data into the first floating gate, further includes: 
 applying a third voltage at the first control gate and applying a fourth voltage at the second control gate so that the channel underneath the first floating gate and the channel underneath the second floating gate are both opened; and    applying a different bias voltage to the two source/drain regions so that electrons in the channel underneath the second floating gate flow and acquire enough energy to generate hot electrons capable of moving into the second floating gate.    
     
     
         12 . The programming method of  claim 10 , wherein the bias voltage applied to the source/drain region on one side of the second stacked gate includes a ground voltage.  
     
     
         13 . A method of programming a double-bit non-volatile memory cell, wherein the double-bit non-volatile memory cell comprises: 
 a substrate;    a first stacked gate and a second stacked gate above the substrate, wherein the first stacked gate includes a first floating gate and a first control gate and the second stacked gate includes a second floating gate and a second control gate;    a doped region located in the substrate between the first stacked gate and the second stacked gate; and    a pair of source/drain regions located in the substrate on each side of the stacked gate pair, wherein the two source/drain regions and the doped region are n-doped; and    the steps of writing data into the first floating gate includes: 
 applying a higher bias voltage at the first control gate and applying a lower bias voltage at the source/drain region on one side of the first stacked gate so that electrons can tunnel into the first floating gate from the source/drain region on one side of the first stacked gate.  
   
     
     
         14 . The programming method of  claim 13 , wherein after the step of writing data into the first floating gate, further includes: 
 applying a higher bias voltage at the second control gate;    applying a lower bias voltage at the source/drain region on one side of the second stacked gate so that electrons can tunnel into the second floating gate from the source/drain region on one side of the second stacked gate.    
     
     
         15 . The programming method of  claim 13 , wherein the bias voltage applied to the source/drain region on one side of the first stacked gate includes a ground voltage.  
     
     
         16 . A method of reading data from a double-bit non-volatile memory cell, wherein the double-bit non-volatile memory cell comprises of: 
 a substrate;    a first stacked gate and a second stacked gate on the substrate, wherein the first stacked gate includes a first floating gate and a first control gate and the second stacked gate includes a second floating gate and a second control gate, the channel underneath the first/the second floating gate is at a first threshold voltage when the first/the second floating gate is in the erased state, and the channel underneath the first/the second floating gate is at a second threshold voltage greater than the first threshold voltage when the first/second floating gate is in the written state;    a doped region in the substrate located between the two stacked gates; and    a pair of source/drain regions located on each side of the stacked gate pair, wherein the two source/drain regions and the doped region are n-doped; and the steps of reading stored data from the first floating gate includes: 
 applying a read bias voltage at the first control gate, wherein the read bias voltage is greater than the first threshold voltage but smaller than the second threshold voltage;  
 applying a transfer bias voltage at the second control gate, wherein the transfer bias voltage is greater than the second threshold voltage so that the channel underneath the second floating gate is opened; and  
 determining the state of the first floating gate by checking the presence or absence of a conductive channel between the two source/drain regions, wherein conduction between the two source/drain regions indicates an unwritten state for the first floating gate while non-conduction indicates a written state.