Fast random access DRAM management method

Abstract

A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

What is claimed is:  
     
         1 . A method of fast random access management of a DRAM-type memory, including the steps of: 
 dividing the memory into memory banks accessible independently in read and write mode;    identifying an address (@b) of the bank concerned by a current request;    comparing the address of the bank concerned by a current request with addresses of N−1 banks previously required, N being an integral number of cycles necessary to execute a request; and    if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and storing the current request until the previous request involving the same bank is executed, otherwise, executing it.    
     
     
         2 . The method of  claim 1 , wherein the suspension operation includes stacking the requests in a memory of first-in/first-out type.  
     
     
         3 . The fast access DRAM management method of  claim 1 , further including for the data reading, the steps of: 
 storing in an output FIFO register the data read during the first M cycles of memory use; and    providing an output datum of the FIFO register, M cycles after each read request.    
     
     
         4 . The fast access DRAM management method of  claim 1 , wherein the memory is periodically refreshed line by line and bank by bank, and including the step of comparing the address of the bank to be refreshed with the addresses of N−1 ongoing requests and of the N following requests and delaying the refreshment if the address of the bank to be refreshed corresponds to one of the bank addresses of the 2N−1 requests.  
     
     
         5 . The fast access DRAM management method of  claim 4 , including the steps of resuming the refreshment and interrupting the request succession after a determined number of refresh cycle interruptions have occurred.  
     
     
         6 . The fast access DRAM management method of  claim 1 , including the steps of: 
 storing N requests following the current request;    if the execution of the current request is suspended, executing one of the following requests not in conflict with the request being executed; and    if the executed request is a read request, arranging back the read information in the order of the executed read requests.    
     
     
         7 . The fast access DRAM management method of  claim 1 , wherein the memory banks are distributed into sets accessible in parallel, whereby each set statistically only needs to process half of the requests.  
     
     
         8 . The fast access DRAM management method of  claim 1 , wherein the memory banks are distributed into several groups, the banks of a same group sharing the same bus, and wherein two requests can be simultaneously transmitted to two distinct groups.