Arrangement of circuit components for interfacing to a network

Abstract

A novel arrangement of circuit components for interfacing the highspeed network such as an Ethernet comprises a first circuit card assembly which includes a microprocessor, a network encoding device, and a first device for performing a transformer function, and a second circuit card assembly which include a second transformer function device and a physical jack interface. Signals are conveyed over an interconnecting bus between the transformer devices, thereby eliminating or reducing interference.

What is claimed is:  
     
         1 . An arrangement for interfacing to a network, comprising: 
 a first circuit card assembly having MP, PHY and a first MAGS embedded thereon in series;    a second MAGS;    a JACK for output to said network and being connected to said second MAGS; and    wherein said first MAGS interfaces to said second MAGS through an interconnecting plane.    
     
     
         2 . The arrangement of  claim 1  wherein said second MAGS and said JACK are both embedded in a single device.  
     
     
         3 . The arrangement of  claim 1  wherein said second MAGS and said JACK are discrete parts.  
     
     
         4 . The arrangement of  claim 1  wherein an input of said second MAGS is connected to a local ground.  
     
     
         5 . The arrangement of  claim 1  wherein an output of said second MAGS comprises dual common-mode chokes.  
     
     
         6 . The arrangement of  claim 1  wherein said first and second MAGs communicate to each other over an interconnecting bus.  
     
     
         7 . The arrangement of  claim 1  wherein said network is an Ethernet network.  
     
     
         8 . An arrangement for interfacing a network, comprising: 
 a first circuit card assembly comprising a MP, a plurality of PHYs each connected to said MP, and a plurality of first MAGSs connected to each of said PHYs respectively;    a plurality of second circuit cards each of which comprises a second MAGS and a JACK for interfacing to said network; and    wherein said each of said first MAGSs interfaces to said second MAGS on one of said second circuit cards through an interconnecting plane.    
     
     
         9 . The arrangement of  claim 8  wherein said second MAGS is connected to a local ground.  
     
     
         10 . The arrangement of  claim 8  wherein said second MAGS comprises dual common-mode chokes.  
     
     
         11 . A circuit card, comprising: 
 an MP,    at least one PHY; and    at least one MAGS connected to said PHY; and    wherein said MP, PHY and MAGS are all embedded together on a single circuit card, and wherein said circuit card communicates with a network via a second circuit card.    
     
     
         12 . The integrated circuit card of  claim 11  wherein said MAGS is adapted to interface to a second set of MAGS that is not located on said circuit card.  
     
     
         13 . The integrated circuit card of  claim 12  wherein said MAGS and said second set of MAGS communicate through an interconnecting bus.  
     
     
         14 . The integrated circuit card of  claim 11  wherein said second set of MAGS is embedded with a JACK for interfacing to a network.  
     
     
         15 .The integrated circuit card of  claim 14  wherein said network is an Ethernet network.  
     
     
         16 . Apparatus comprising a network and a microprocessor for communicating with said network, and a communications path from said microprocessor to said network, the communications path including a first and second set of MAGS.  
     
     
         17 . The apparatus of  claim 16  wherein said first and second set of MAGS is are located on different CCAs.  
     
     
         18 . The apparatus of  claim 17  wherein said second of MAGS is connected to a local ground.