Data processing device with memory coupling unit

Abstract

A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

1 . Data processing unit with a register file having a plurality of registers, a memory having a plurality of n-bit input/output ports, and a coupling unit for coupling said memory with said register file, a memory address and select unit for addressing said memory, wherein said coupling unit comprises: 
 a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus,    first couplers for coupling each port of said memory with at least one of said sub-busses, and    second couplers for coupling said register file with at least one of said sub-busses.    
     
     
         2 . Data processing unit according to  claim 1 , wherein said memory comprises a plurality of memory banks.  
     
     
         3 . Data processing unit according to  claim 1 , wherein the first couplers selectively couple each port with one of said sub-busses.  
     
     
         4 . Data processing unit according to  claim 1 , wherein each of the second couplers selectively couples the register file with one of said sub-busses.  
     
     
         5 . Data processing unit according to  claim 1 , wherein said memory address and select unit controls single byte, word or multiple byte access.  
     
     
         6 . Data processing unit according to  claim 3 , wherein said second couplers comprise an alignment unit which based upon said access type couples either said bus with a plurality of selectable registers of said register file in parallel or one of said sub-busses with a selectable register of said register file.  
     
     
         7 . Data processing unit according to  claim 1 , wherein said first couplers comprise tri-state buffers for coupling the output lines of said ports with respective lines of said bus.  
     
     
         8 . Data processing unit according to  claim 1 , wherein said first couplers comprise multiplexers for coupling the output lines of said ports with respective lines of said bus.  
     
     
         9 . Data processing unit according to  claim 3 , wherein said memory comprises a plurality of memory banks and depending on the access type said memory address and select unit only selects the memory bank needed for the respective access.  
     
     
         10 . Data processing unit according to  claim 1 , wherein said register file comprises a plurality of registers, whereby a number of registers being accessible in parallel, said registers having a combined bit width which is at least equal to the sum of the bit width of each memory bank port, thereby forming a multiple n-bit interface to said register file.  
     
     
         11 . Data processing unit according to  claim 9 , said memory comprises even and odd memory banks and said bus comprises even and odd sub-busses, whereby said first couplers are bi-directional tri-state drivers coupling each odd memory bank with each even sub-bus and each even memory bank with each even sub-bus and whereby the second couplers couple the sub-busses with the register file interface in such a way, that said port of any memory bank can be coupled with any n-bit part of said register file interface.  
     
     
         12 . Data processing unit according to  claim 1 , wherein said memory comprises a plurality of memory banks, wherein each bank comprises a memory input/output port having a m-byte width, whereby 2m-bytes data are addressed by said address and select unit in each memory bank and further select lines select one of the two m-byte data to be output at said port.  
     
     
         13 . Data processing unit according to  claim 1 , wherein said memory comprises a plurality of memory banks each organized to output a memory row having multiple m-bytes, and multiple multiplexers to select for each m-byte portion one of said memory banks.  
     
     
         14 . Data processing unit according to  claim 1 , wherein the first couplers select a predefined number of bits equal to the number of bits of said bus and the second coupler reorder the selected bits from said bus.  
     
     
         15 . Data processing unit according to  claim 14 , wherein said memory comprises at least four n-bit ports and the first couplers couple 2n-bits of said memory with said bus and said second couplers comprise a plurality of barrel shifters being controlled by an address signal.  
     
     
         16 . Data processing unit according to  claim 1 , wherein said busses comprise a plurality of bus lines and at least one bus line is coupled with a bus holder.  
     
     
         17 . Data processing unit comprising a first and a second register file having a plurality of registers, a memory having a plurality of n-bit input/output ports, a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each port selectively with one of said sub-busses, second couplers for coupling said first register file with said bus, and third couplers for coupling said second register file with said bus.  
     
     
         18 . Data processing unit according to  claim 17 , wherein said memory comprises a plurality of memory banks.  
     
     
         19 . Data processing unit according to  claim 17 , wherein said memory address and select unit controls single byte, word or multiple byte access.  
     
     
         20 . Data processing unit according to  claim 19 , wherein said second and third couplers comprise an alignment unit which based upon said access type couples either said bus with a plurality of selectable registers of said register files in parallel or one of said sub-busses with a selectable register of said register files.  
     
     
         21 . Data processing unit according to  claim 17 , wherein said first couplers comprise tri-state buffers for coupling the output lines of said ports with respective lines of said bus.  
     
     
         22 . Data processing unit according to  claim 17 , wherein said first couplers comprise multiplexers for coupling the output lines of said ports with respective lines of said bus.  
     
     
         23 . Data processing unit according to  claim 19 , wherein said memory comprises a plurality of memory banks and depending on the access type said memory address and select unit only selects the memory bank needed for the respective access.  
     
     
         24 . Data processing unit according to  claim 17 , wherein each register file comprises a plurality of registers, whereby a number of registers being accessible in parallel, said registers having a combined bit width which is at least equal to the sum of the bit width of each memory bank port, thereby forming a multiple n-bit interface to said register file.  
     
     
         25 . Data processing unit according to  claim 24 , said memory comprises even and odd memory banks and said bus comprises even and odd sub-busses, whereby said first couplers are bi-directional tri-state drivers coupling each odd memory bank with each even sub-bus and each even memory bank with each even sub-bus and whereby the second couplers couple the sub-busses with the register file interface in such a way, that said port of any memory bank can be coupled with any n-bit part of said register file interface.  
     
     
         26 . Data processing unit according to  claim 17 , wherein said memory comprises a plurality of memory banks, wherein each bank comprises a memory input/output port having a n-byte width, whereby 2n-bytes data are addressed by said address and select unit in each memory bank and further select lines select one of the two n-byte data to be output at said port.  
     
     
         27 . Data processing unit according to  claim 17 , wherein said memory comprises a plurality of memory banks each organized to output a memory row having multiple n-bytes, and multiple multiplexers to select for each n-byte portion one of said memory banks.  
     
     
         28 . Data processing unit according to  claim 17 , wherein the first couplers select a predefined number of bits equal to the number of bits of said bus and the second coupler reorder the selected bits from said bus.  
     
     
         29 . Data processing unit according to  claim 28 , wherein said memory comprises at least four n-bit ports and the first couplers couple 2n-bits of said memory with said bus and said second couplers comprise a plurality of barrel shifters being controlled by an address signal.  
     
     
         30 . Data processing unit according to  claim 17 , wherein said busses comprise a plurality of bus lines and at least one bus line is coupled with a bus holder.  
     
     
         31 . Data processing unit comprising a first and a second register file having a plurality of registers, a first and second memory each having a plurality of n-bit input/output ports, a first bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each port of said first memory selectively with one of said sub-busses, second couplers for coupling said first register file with said first bus, a second bus having a bus width of at least 2n-bits forming at least a third and fourth sub-bus, third couplers for coupling each port of said second memory selectively with one of said sub-busses, fourth couplers for coupling said second register file with said second bus, and a bus-coupler for coupling said first and second bus.  
     
     
         32 . Data processing unit according to  claim 31 , wherein said memories having a plurality of memory banks.  
     
     
         33 . Data processing unit according to  claim 31 , wherein said memory address and select unit controls single byte, word or multiple byte access.  
     
     
         34 . Data processing unit according to  claim 32 , wherein said second and fourth couplers comprise an alignment unit which based upon said access type couples either said first or second bus with a plurality of selectable registers of said first or second register file in parallel or one of said sub-busses with a selectable register of one of said register files.  
     
     
         35 . Data processing unit according to  claim 31 , wherein said first and third couplers comprise tri-state buffers for coupling the output lines of said ports with respective lines of said first or second bus.  
     
     
         36 . Data processing unit according to  claim 31 , wherein said first and third couplers comprise multiplexers for coupling the output lines of said ports with respective lines of said first or second bus.  
     
     
         37 . Data processing unit according to  claim 32 , wherein said memories comprise a plurality of memory banks and depending on the access type said memory address and select unit only selects the memory bank needed for the respective access.  
     
     
         38 . Data processing unit according to  claim 31 , wherein said first or second register file comprises a plurality of registers, whereby a number of registers being accessible in parallel, said registers having a combined bit width which is at least equal to the sum of the bit width of each port in said first or second memory, thereby forming a multiple n-bit interface to said first or second register file.  
     
     
         39 . Data processing unit according to  claim 37 , said first or second memory comprises even and odd memory banks and said first or second bus comprises even and odd sub-busses, whereby said first couplers are bi-directional tri-state drivers coupling each odd memory bank with each even sub-bus and each even memory bank with each even sub-bus and whereby the second or fourth couplers couple the sub-busses with the first or second register file interface in such a way, that said port of any memory bank can be coupled with any n-bit part of said first or second register file interface.  
     
     
         40 . Data processing unit according to  claim 31 , wherein said first or second memory comprises a plurality of memory banks, wherein each bank comprises a memory input/output port having a n-byte width, whereby 2n-bytes data are addressed by said address and select unit in each memory bank and further select lines select one of the two n-byte data to be output at said port.  
     
     
         41 . Data processing unit according to  claim 31 , wherein said first or second memory comprises a plurality of memory banks each organized to output a memory row having multiple n-bytes, and multiple multiplexers to select for each n-byte portion one of said memory banks.  
     
     
         42 . Data processing unit according to  claim 31 , wherein the first and third couplers select a predefined number of bits equal to the number of bits of said bus and the second and fourth couplers reorder the selected bits from said bus.  
     
     
         43 . Data processing unit according to  claim 42 , wherein said first and second memory each comprise at least four n-bit ports and the first and second couplers couple 2n-bits of said memory with said first and second bus and said third and fourth couplers comprise a plurality of barrel shifters being controlled by an address signal.  
     
     
         44 . Data processing unit according to  claim 31 , wherein said busses comprise a plurality of bus lines and at least one bus line is coupled with a bus holder.  
     
     
         45 . Data processing unit according to  claim 44 , wherein said bus holder comprises a first and a second inverter coupled in series, whereby the input of said first inverter and the output of said second inverter are coupled with said bus line.  
     
     
         46 . Data processing unit according to  claim 45 , wherein said second inverter is weaker than said first inverter.