Method for avoiding the ion penetration with the plasma doping

Abstract

First of all, a semiconductor substrate is provided. Then a gate oxide layer having an uniform thickness is formed on the semiconductor substrate by way of using thermal oxidation. Subsequently, a doping layer is formed on the gate oxide layer by a plasma doped process. Next, forming a poly-layer on the doping layer of the gate oxide layer, wherein the poly-layer has an ions-distribution. Afterward, defining the poly-layer to form a poly-gate. The P-type ions are then implanted into the poly-gate and the substrate by way of using a self-aligned process. Finally, performing a thermal annealing process to form a uniform ion-implanting region and a poly-gate having a lower contact-resistance.

What is claimed is:  
     
         1 . A method for doping a dielectric layer, said method comprising: 
 providing a substrate;    forming a dielectric layer on said substrate; and    performing a plasma doping process to form a doping layer on said dielectric layer.    
     
     
         2 . The method according to  claim 1 , wherein the step for forming said dielectric layer comprises a thermal process.  
     
     
         3 . The method according to  claim 1 , wherein said plasma doping process comprises a pulsed plasma doping process.  
     
     
         4 . A method for forming a gate, said method comprising: 
 providing a substrate;    forming a dielectric layer on said substrate;    performing a plasma doping process to form an absorbed layer on said dielectric layer;    forming an ion-barrier layer in said absorbed layer; and    forming and defining a gate on said ion-barrier layer.    
     
     
         5 . The method according to  claim 4 , wherein said plasma doping process comprises a pulsed plasma doping process.  
     
     
         6 . The method according to  claim 4 , wherein said absorbed layer comprises an nitrogen.  
     
     
         7 . The method according to  claim 4 , wherein the step for forming said ion-barrier layer comprises a thermal process.  
     
     
         8 . A method for forming a gate, said method comprising: 
 providing a substrate;    forming a dielectric layer on said substrate;    performing a plasma doping process to form an absorbed layer on said dielectric layer;    forming a first conductor layer to react with said absorbed layer, so as to form a second conductor layer having an absorbed-ions distribution on said dielectric layer; and    forming and defining said second conductor layer to form a gate having said absorbed-ions distribution on said dielectric layer on said dielectric layer.    
     
     
         9 . The method according to  claim 8 , wherein said plasma doping process comprises a pulsed plasma doping process.  
     
     
         10 . The method according to  claim 8 , wherein said absorbed layer comprises an nitrogen.  
     
     
         11 . A method for forming a gate, said method comprising: 
 providing a silicon substrate;    forming an oxide layer on said silicon substrate;    performing a pulsed plasma doping process to absorb an nitrogen on said oxide layer;    forming an ion-barrier layer on said oxide layer by way of using a thermal oxidation process;    forming and defining a gate on said ion-barrier layer; and    forming an ion-doping region in said gate and an ion-doping region in said silicon substrate.    
     
     
         12 . The method according to  claim 11 , wherein the energy of said pulsed plasma doping process is about 200 eV to 10000 eV.  
     
     
         13 . The method according to  claim 11 , wherein the dosage of said nitrogen is about 10 14 /cm 2  to 10 17 /cm 2 .  
     
     
         14 . The method according to  claim 11 , wherein the temperature of said thermal oxidation process is about 800° C. to 1000° C.  
     
     
         15 . The method according to  claim 11 , wherein said ion-barrier layer comprises an nitride oxide.  
     
     
         16 . The method according to  claim 11 , wherein the step for forming said ion-doping region comprises a self-aligned implanting process.  
     
     
         17 . The method according to  claim 11 , wherein the step for forming said ion-doping region comprises a thermal annealing process.  
     
     
         18 . The method according to  claim 11 , wherein said ion-doping region comprises a P-type ion.  
     
     
         19 . The method according to  claim 18 , wherein said P-type ion comprises a boron ion.  
     
     
         20 . A method for forming a gate, said method comprising: 
 providing a silicon substrate;    forming an oxide layer on said silicon substrate;    performing a pulsed plasma doping process to form an nitrogen-absorbed layer on said oxide layer;    forming a first conductor layer to react with said nitrogen-absorbed layer, so as to form a second conductor layer having an ions-absorbed distribution on said oxide layer;    defining said second conductor layer to form a gate having said ions-absorbed distribution on said oxide layer; and    forming an ion-doping region in said gate and an ion-doping region in said silicon substrate by way of using an implanting process.    
     
     
         21 . The method according to  claim 20 , wherein the energy of said pulsed plasma doping process is about 200 eV to 10000 eV.  
     
     
         22 . The method according to  claim 20 , wherein the dosage of said nitrogen is about 10 14 /cm 2  to 10 17 /cm 2 .  
     
     
         23 . The method according to  claim 20 , wherein said conductor layer comprises a silicon nitride.  
     
     
         24 . The method according to  claim 20 , wherein said implanting process comprises a self-aligned implanting process.  
     
     
         25 . The method according to  claim 20 , wherein the step for forming said ion-doping region comprises a thermal annealing process.  
     
     
         26 . The method according to  claim 20 , wherein said ion-doping region comprises a P-type ion.  
     
     
         27 . The method according to  claim 26 , wherein said P-type ion comprises a boron ion.  
     
     
         28 . A method for forming a gate, said method comprising: 
 providing a silicon substrate;    forming a gate oxide layer on said silicon substrate;    performing a pulsed plasma doping process having an energy about 200 eV to 10000 eV to absorb an nitrogen on said gate oxide layer;    forming an silicon nitride oxide layer on said gate oxide layer by way of using a thermal oxidation process;    forming and defining a gate on said silicon nitride oxide layer; and    forming a doping region of boron in said gate and a doping region of boron in said silicon substrate.    
     
     
         29 . The method according to  claim 28 , wherein the dosage of said nitrogen is about 10 14 /cm 2  to 10 17 /cm 2 .  
     
     
         30 . The method according to  claim 28 , wherein the temperature of said thermal oxidation process is about 800° C. to 10000° C.  
     
     
         31 . A method for forming a gate, said method comprising: 
 providing a silicon substrate;    forming a gate oxide layer on said silicon substrate;    performing a pulsed plasma doping process having an energy about 200 eV to 10000 eV to form an nitrogen-absorbed layer on said gate oxide layer;    forming a first conductor layer to react with said nitrogen-absorbed layer, so as to form a second conductor layer having an silicon nitride on said gate oxide layer;    defining said second conductor layer to form a gate having said silicon nitride distribution on said gate oxide layer; and    forming a doping region of boron in said gate and a doping region of boron in said silicon substrate by way of using an implanting process.    
     
     
         32 . The method according to claim  31 , wherein the dosage of said nitrogen is about 10 14 /cm 2  to 10 17 /cm 2 .