Method for forming self-aligned local-halo metal-oxide-semiconductor device

Abstract

A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

What is claimed is:  
     
         1 . A method for forming a self-aligned local-halo metal-oxide-semiconductor device, comprising: 
 providing a semiconductor substrate with a first conductive type having a plurality of shallow trench isolation formed therein;    sequentially forming a gate oxide and a gate electrode between each pair of said shallow trench isolation over said substrate;    forming a first sidewall spacer along each side of said gate electrode;    forming a second sidewall spacer along one side of each said first sidewall spacer;    forming a raised source/drain upward on said substrate between each said shallow trench isolation and each said second sidewall spacer;    removing each said second sidewall spacer;    forming a lightly doped diffusion region with a second conductive type being opposite with said first conductive type between each said raised source/drain and said gate electrode in said substrate; and    forming a halo diffusion region with said first conductive type surrounding said lightly doped diffusion region.    
     
     
         2 . The method of  claim 1 , wherein said first conductive type is either of N type and P type.  
     
     
         3 . The method of  claim 1 , wherein said first sidewall spacer comprises conformal silicon dioxide.  
     
     
         4 . The method of  claim 1 , wherein said second sidewall spacer comprises silicon nitride.  
     
     
         5 . The method of  claim 1 , wherein said raised source/drain has a thickness with about 400˜1000 angstroms.  
     
     
         6 . The method of  claim 1 , wherein said raised source/drain comprises semiconductor material.  
     
     
         7 . The method of  claim 6 , wherein said raised source/drain comprises selective epitaxial growth (SEG) silicon.  
     
     
         8 . The method of  claim 7 , wherein said selective epitaxial growth (SEG) silicon is formed by way of ultra-high vacuum chemical vapor deposition (UHVCVD) method.  
     
     
         9 . The method of  claim 6 , wherein said raised source/drain comprises selective epitaxial growth (SEG) silicon germanium alloy.  
     
     
         10 . The method of  claim 9 , wherein said selective epitaxial growth (SEG) silicon germanium alloy is formed by way of ultra-high vacuum chemical vapor deposition method.  
     
     
         11 . The method of  claim 1 , wherein said second sidewall spacer is removed by way of wet etching with H 3 PO 4  aqueous solution.  
     
     
         12 . The method of  claim 1 , wherein said lightly doped diffusion region is formed by way of arsenic ion implantation with an implantation energy of 5 to 15 Kev at an implantation dose of about 5×10 13  to 5×10 15  ions/cm 2 .  
     
     
         13 . The method of  claim 12 , wherein said halo diffusion region is formed by way of boron ion implantation with an implantation energy of 15 to 25 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         14 . The method of  claim 13 , wherein said halo diffusion region is formed by way of BF 2   +  ion implantation with an implantation energy of 30 Kev to 40 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         15 . The method of  claim 1 , wherein said lightly doped diffusion region is formed by way of boron ion implantation with an implantation energy of 5 Kev to 15 Kev at an implantation dose of about 5×10 13  to 5×10 15  ions/cm 2 .  
     
     
         16 . The method of  claim 15 , wherein said halo diffusion region is formed by way of arsenic ion implantation with an implantation energy of 130 Kev to 150 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         17 . A method for forming a self-aligned local-halo metal-oxide-semiconductor device with raised source/drain, comprising: 
 providing a semiconductor substrate with a first conductive type having a plurality of shallow trench isolation formed therein;    sequentially forming a gate oxide and a gate electrode between each pair of said shallow trench isolation over said substrate;    forming a sidewall spacer of silicon dioxide along each side of said gate electrode;    forming a sidewall spacer of silicon nitride along one side of each said sidewall spacer of silicon dioxide;    forming a raised source/drain of selective epitaxial growth semiconductor material upward on said substrate between each said shallow trench isolation and each said sidewall spacer of silicon nitride;    removing each said sidewall spacer of silicon nitride;    forming a lightly doped diffusion region with a second conductive type being opposite with said first conductive type between each said raised source/drain and said gate electrode in said substrate; and    forming a halo diffusion region with said first conductive type surrounding each said lightly doped diffusion region.    
     
     
         18 . The method of  claim 17 , wherein said first conductive type is either of N type and P type.  
     
     
         19 . The method of  claim 17 , wherein said raised source/drain of selective epitaxial growth semiconductor material is formed by way of ultra-high vacuum chemical vapor deposition method (UHVCVD).  
     
     
         20 . The method of  claim 19 , wherein said raised source/drain comprises silicon.  
     
     
         21 . The method of  claim 19 , wherein said raised source/drain comprises silicon germanium alloy.  
     
     
         22 . The method of  claim 17 , wherein said sidewall spacer of silicon nitride is removed by way of wet etching with H 3 PO 4  aqueous solution.  
     
     
         23 . The method of  claim 17 , wherein said lightly doped diffusion region is formed by way of arsenic ion implantation with an implantation energy of 5 Kev to 15 Kev at an implantation dose of about 5×10 13  to 5×10 15  ions/cm 2 .  
     
     
         24 . The method of  claim 23 , wherein said halo diffusion region is formed by way of boron ion implantation with an implantation energy of 15 Kev to 25 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         25 . The method of  claim 23 , wherein said halo diffusion region is formed by way of BF 2   +  ion implantation with an implantation energy of 30 Kev to 40 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         26 . The method of  claim 17 , wherein said lightly doped diffusion region is formed by way of boron ion implantation with an implantation energy of 5 Kev to 15 Kev at an implantation dose of about 5×10 13  to 5×10 15  ions/cm 2 .  
     
     
         27 . The method of  claim 26 , wherein said halo diffusion region is formed by way of arsenic ion implantation with an implantation energy of 130 Kev to 150 Kev at an implantation dose of about 1×10 13  to 5×10 14  ions/cm 2 .  
     
     
         28 . A self-aligned local-halo metal-oxide-semiconductor device with raised source/drain, comprising: 
 a semiconductor substrate with a first conductive type;    a plurality of shallow trench isolation formed in said substrate;    a gate electrode with a pair of conformal sidewall spacers formed between each pair of said shallow trench isolation on said substrate;    a pair of raised source/drain formed upward on said substrate and between each said shallow trench isolation and each said sidewall spacer;    a pair of lightly doped diffusion region with a second conductive type being opposite to said first conductive type, each of which formed between each said raised source/drain and said gate electrode in said substrate; and    a pair of halo diffusion region with said first conductive type, each of which formed surrounding each said lightly doped diffusion region.    
     
     
         29 . The device of  claim 28 , wherein said first conductive type is either of N type and P type.  
     
     
         30 . The device of  claim 28 , wherein said raised source/drain has a thickness about 400˜1000 angstroms.  
     
     
         31 . The device of  claim 28 , wherein said raised source/drain comprises selective epitaxial growth silicon.  
     
     
         32 . The device of  claim 28 , wherein said raised source/drain comprises selective epitaxil growth silicon germanium alloy.  
     
     
         33 . The device of  claim 28 , wherein said lightly doped diffusion region has an impurity concentration about 5×10 13  to 5×10 15  ions/cm 2 .  
     
     
         34 . The device of  claim 28 , wherein said halo diffusion region has an impurity concentration about 1×10 13  to 5×10 14  ions/cm 2 .