Semiconductor device and method of fabricating the same

Abstract

A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.

What is claimed is:  
     
         1 . A semiconductor device comprising: 
 a semiconductor substrate having a major surface;    a first region being formed on said major surface of said semiconductor substrate;    a first impurity region being formed on a surface of said first region;    a first conductor layer being formed on a surface of said first impurity region;    a second conductor layer being formed on said first conductor layer;    a third conductor layer being formed on said second conductor layer;    a first insulator layer being formed on said semiconductor substrate to enclose said first to third conductor layers; and    a first conductor region being formed on said first insulator layer and electrically connected with said third conductor layer,    said first conductor layer containing silicon,    said second conductor layer containing a compound of silicon and a prescribed metal,    said third conductor layer containing prescribed said metal or a compound of said metal.    
     
     
         2 . The semiconductor device in accordance with  claim 1 , wherein said first insulator layer has a first contact hole exposing a surface of said first conductor layer, and 
 said second and third conductor layers are formed in said first contact hole.    
     
     
         3 . The semiconductor device in accordance with  claim 2 , further including: 
 a pair of source/drain regions being provided on a major surface of said first region at a space, and    a gate electrode being formed on a region of said semiconductor substrate being held between respective ones of said source/drain regions with a gate insulator film interposed, wherein 
 one of said source/drain regions includes said first impurity region, and  
 said first conductor layer is formed in the vicinity of said gate electrode to partially cover said gate electrode while being electrically insulated from said gate electrode.  
   
     
     
         4 . The semiconductor device in accordance with  claim 3 , wherein said first region includes a plurality of element forming regions and an element isolation region electrically insulating said element forming regions from each other, and 
 said gate electrode includes a first gate electrode portion extending on each said element forming region and a second gate electrode portion being connected with said first gate electrode portion and extending on said element isolation region,    said semiconductor device further including a second protective layer being formed under said first insulator layer to cover said second gate electrode portion.    
     
     
         5 . The semiconductor device in accordance with  claim 1 , further including: 
 a second impurity region being formed on a major surface of said first region at a space from said first impurity region,    a fourth conductor layer, containing silicon, being formed on a surface of said second impurity region,    a first protective layer being formed to cover a surface of said first conductor region, and    a second insulator layer being formed on said first insulator layer to cover said first protective layer, wherein    said first and second insulator layers have a second contact hole exposing a surface of said fourth conductor layer,    said semiconductor device further including: 
 a fifth conductor layer, containing a compound of silicon and prescribed said metal, being formed in said second contact hole and electrically connected with said fourth conductor layer,  
 a sixth conductor layer, containing prescribed said metal or a compound of said metal, being formed on said fifth conductor layer in said second contact hole, and  
 a second conductor layer being formed on said second insulator layer and electrically connected with said sixth conductor layer.  
   
     
     
         6 . The semiconductor device in accordance with  claim 5 , wherein the other one of said pair of source/drain regions includes said second impurity region, and 
 said gate electrode is formed on a region being held between said first and second impurity regions.    
     
     
         7 . The semiconductor device in accordance with  claim 5 , further including: 
 a second region being formed on said major surface of said semiconductor substrate and electrically insulated from said first region,    a third impurity region being formed on a surface of said second region, and    a third insulator layer being formed on said second insulator layer to cover said first and second regions, wherein    said first and second insulator layers have a third contact hole exposing a surface of said third impurity region,    said third insulator layer has a fourth contact hole communicating with said third contact hole, and    said third insulator layer has a fifth contact hole exposing a surface of said second conductor region,    said semiconductor device further including: 
 a first columnar conductor being formed in said third contact hole and electrically connected with said third impurity region,  
 a second columnar conductor being formed in said fourth contact hole and electrically connected with said first columnar conductor,  
 a third columnar conductor being formed in said fifth contact hole,  
 a first wiring layer being electrically connected with said second columnar conductor and formed on said third insulator layer, and  
 a second wiring layer being electrically connected with said third columnar conductor and formed on said third insulator layer.  
   
     
     
         8 . The semiconductor device in accordance with  claim 7 , wherein said first and second wiring layers are formed by the same layer.  
     
     
         9 . The semiconductor device in accordance with  claim 7 , further including a relay conductor, larger in sectional area than said first columnar conductor, being formed on said second insulator layer to intervene between said first and second columnar conductors.  
     
     
         10 . The semiconductor device in accordance with  claim 9 , wherein said relay conductor is formed by the same layer as said second conductor region.  
     
     
         11 . The semiconductor device in accordance with  claim 1 , further including: 
 a third region being formed on said major surface of said semiconductor substrate and electrically insulated from said first region,    a fourth impurity region being formed on a surface of said third region, and    a fourth insulator layer being formed on said first insulator layer to cover said first and third regions, wherein    said first insulator layer has a sixth contact hole exposing a surface of said fourth impurity region,    said fourth insulator layer has a seventh contact hole communicating with said sixth contact hole, and    said fourth insulator layer has an eighth contact hole exposing a surface of said first conductor region,    said semiconductor device further including: 
 a fourth columnar conductor being formed in said sixth contact hole and electrically connected with said fourth impurity region,  
 a fifth columnar conductor being formed in said seventh contact hole and electrically connected with said fourth columnar conductor,  
 a sixth columnar conductor being formed in said eighth contact hole, and  
 a third wiring layer being electrically connected with said fifth and sixth columnar conductors and formed on said fourth insulator layer.  
   
     
     
         12 . A method of fabricating a semiconductor device comprising steps of: 
 forming a first impurity region on a major surface of a semiconductor substrate;    forming a first conductor layer containing silicon on a surface of said first impurity region;    forming a conductive material layer containing a prescribed metal on said first conductor layer and heat-treating the same thereby forming a second conductor layer containing a compound of said silicon being contained in said conductor layer and prescribed said metal;    forming a third conductor layer containing said metal or a compound of said metal on said second conductor layer;    forming a first insulator layer on said semiconductor substrate to enclose said first to third conductor layers; and    forming a first conductor region being electrically connected with said third conductor layer on said first insulator layer.    
     
     
         13 . The method of fabricating a semiconductor device in accordance with  claim 12 , wherein said steps of forming said second and third conductor layers include steps of: 
 forming a first contact hole exposing a surface of said first conductor layer in said first insulator layer, and    forming said second and third conductor layers in said first contact hole.    
     
     
         14 . The method of fabricating a semiconductor device in accordance with  claim 13 , further including steps of: 
 forming a gate electrode on said major surface of said semiconductor substrate with a gate insulator film interposed, and    forming a pair of source/drain regions on said major surface of said semiconductor substrate both sides of said gate electrode, wherein    said step of forming said source/drain regions includes a step of forming said first impurity region, and    said step of forming said first conductor layer includes a step of forming said first conductor layer in the vicinity of said gate electrode to partially enclose said gate electrode while being electrically insulated from said gate electrode.    
     
     
         15 . The method of fabricating a semiconductor device in accordance with  claim 14 , further including steps of: 
 forming a plurality of element forming regions and an element isolation region electrically insulating said element forming regions from each other in said first region,    forming a first gate electrode portion extending on each said element forming region and a second gate electrode portion being connected with said first gate electrode portion and extending on said element isolation region as said gate electrode, and    forming a second protective layer to cover said gate electrode,    in advance of said step of forming said first insulator layer,    said method further including steps of: 
 forming an opening exposing a surface of said second protective layer in said first insulator layer being located on each said element forming region including a portion on said first gate electrode portion, and  
 removing exposed said second protective layer thereby exposing a surface of said element forming region including said first gate electrode portion.  
   
     
     
         16 . The method of fabricating a semiconductor device in accordance with  claim 12 , further including steps of: 
 forming a second impurity region on a major surface of said first region of said semiconductor substrate at a space from said first impurity region, and    forming a fourth conductor layer containing silicon on said second impurity region,    in advance of said step of forming said first insulator layer,    said method further including steps of: 
 forming a first protective layer on a surface of said first conductor region,  
 forming a second insulator layer on said first insulator layer to cover said first protective layer,  
 forming a second contact hole exposing a surface of said fourth conductor layer in said first and second insulator layers,  
 forming a conductive material layer containing prescribed said metal in said second contact hole and heat-treating the same thereby forming a fifth conductor layer containing a compound of said silicon being contained in said fourth conductor layer and prescribed said metal,  
 forming a sixth conductor layer containing said metal or a compound of said metal on said fifth conductor layer in said second contact hole, and  
 forming a second conductor region being electrically connected with said sixth conductor layer on said second insulator layer.  
   
     
     
         17 . The method of fabricating a semiconductor device in accordance with  claim 16 , wherein said step of forming said pair of source/drain regions includes said steps of forming said first and second impurity regions, and 
 said step of forming said gate electrode includes a step of forming said gate electrode on a region of said semiconductor substrate being held between said first and second impurity regions.    
     
     
         18 . The method of fabricating a semiconductor device in accordance with  claim 16 , further including steps of: 
 forming a first region including said first and second impurity regions on said major surface of said semiconductor substrate, and    forming a second region being electrically insulated from said first region on said major surface of said semiconductor substrate,    forming a third impurity region on said major surface of said second region,    in advance of said step of forming said first insulator layer, and    forming a third contact hole exposing a surface of said third impurity region in said first and second insulator layers,    forming a first columnar conductor in said third contact hole,    forming a third insulator layer on said second insulator layer to cover surfaces of said second conductor region and said first columnar conductor,    forming fourth and fifth contact holes exposing surfaces of said first columnar conductor and said second conductor region respectively in said third insulator layer,    forming a second columnar conductor in said fourth contact hole,    forming a third columnar conductor in said fifth contact hole, and    forming first and second wiring layers being electrically connected with said third and second columnar conductors respectively on said third insulator layer,    after said step of forming said second insulator layer.    
     
     
         19 . The method of fabricating a semiconductor device in accordance with  claim 18 , further including a step of forming a relay conductor, larger in sectional area than said first columnar conductor, being electrically connected with said first columnar conductor on said second insulator layer between said steps of forming said first columnar conductor and forming said second columnar conductor.  
     
     
         20 . The method of fabricating a semiconductor device in accordance with  claim 19 , wherein said step of forming said relay conductor is carried out simultaneously with said step of forming said second conductor region.