System and method for providing a low power receiver design

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

1 . A receiver partially implemented on an integrated circuit chip, the receiver comprising: 
 means on the chip for receiving a plurality of channels of signals in a radio frequency telecast band;    first mixer on the chip to which the television signals are applied;    a first bandpass filter off the chip coupled onto the chip to the output of the first mixer; the first filter having a first pass band;    a first local oscillator (LO) on the chip coupled to the first mixer, the first LO having a variable frequency;    means on the chip for adjusting the first LO to select one of the channels and shift the selected channel to the first pass band;    a second mixer on the chip to which the selected channel is applied after the first mixer;    a second LO on the chip coupled to the second mixer, the second LO having a fixed frequency that shifts the selected channel to an intermediate frequency; and    means for demodulating the selected channel.    
     
     
         2 . The television receiver of  claim 1 , additionally comprising a second bandpass filter off the chip coupled onto the chip to the output of the second mixer; the second filter having a second pass band, the second LO having a frequency that shifts the selected channel to the second pass band.  
     
     
         3 . The television receiver of  claim 1 , in which the receiving means, the first LO, and the second LO have differential outputs, the first and second mixers have differential inputs and outputs, and the first bandpass filter has a differential input and a differential output.  
     
     
         4 . An integrated receiver comprising: 
 a substrate providing a physical medium upon which a receiver circuit is disposed;    a first local oscillator;    a second local oscillator;    a mixer having its circuit elements disposed upon the substrate for converting a received signal to a first IF using the first local oscillator's output to mix the received signal with;    a first buffer amplifier having its circuit elements disposed upon the substrate cascaded after the mixer;    an external first differential filter assembly coupled to the first buffer amplifier output for removing an image distortion from the first IF and removing unwanted channels;    a second buffer amplifier having its circuit elements disposed upon the substrate coupled to the external first differential filter assembly output;    a first I/Q mixer disposed upon the substrate for converting the first IF to a second IF I and Q signal and rejecting a first IF image distortion;    a polyphase circuit for combining the second IF I and Q signals into a second IF signal;    a third buffer amplifier having its circuit elements disposed upon the substrate and cascaded with the polyphase circuit; and    an external second differential filter assembly coupled to the third buffer amplifier output for removing an image distortion from the second IF and removing unwanted channels;    whereby frequency conversion, channel selectivity and image rejection are performed on the integrated circuit.    
     
     
         5 . The integrated receiver of  claim 4  additionally comprising an AGC circuit having its circuit elements disposed upon the substrate, cascaded after the external second differential filter assembly.  
     
     
         6 . The integrated receiver of  claim 4  additionally comprising a programable gain attenuator and LNA circuit having its circuit elements disposed upon the substrate, cascaded in front of the first mixer.  
     
     
         7 . The integrated receiver of  claim 4  wherein the substrate is silicon.  
     
     
         8 . The integrated receiver of  claim 4  wherein the substrate comprises devices fabricated according to standard CMOS processing.  
     
     
         9 . The integrated receiver of  claim 4  further comprising interconnection by differential signal transmission lines.