PLL device and programmable frequency-division device

Abstract

A PLL device includes a programmable frequency-division device 111 that divides the frequency of the output of a voltage-controlled oscillator 112, a reference signal generating means 105 that generates a first reference signal and a second reference signal having different phases, a first comparator 106 that compares the phases of the first reference signal and the output of the programmable frequency-division device 111, a second comparator 110 that compares the phases of the second reference signal and the output of the programmable frequency-division device 111, a detector 118 that detects the locked state, and a control unit 117. With this structure, when the state is not locked, phase comparisons are performed by a plurality of comparators at different timings, so the locking time is shortened because more than one phase comparison is performed in one period of the reference signal. In the locked state, the phase comparisons are performed by one comparator, mitigating the increase in power consumption due to having multiple loops.

What is claimed is:  
     
         1 . A PLL device, comprising: 
 a programmable frequency-division device ( 113 ,  114 ,  115 ,  116 ) that divides the frequency of the output of a voltage-controlled oscillator ( 112 );    a reference signal generating means ( 101 ,  102 ,  103 ,  104 ) generating a first reference signal and a second reference signal that differ in phase;    a first comparator ( 106 ) that compares the phases of said first reference signal and the output of said programmable frequency-division device;    a second comparator ( 110 ) that compares the phases of said second reference signal and the output of said programmable frequency-division device;    a detector ( 118 ,  120 ,  122 ,  124 ) for detecting a locked state; and    a control unit ( 117 );    wherein the control unit ( 117 ) causes both said first comparator ( 106 ) and said second comparator ( 110 ) to perform comparisons when the state is not locked, and causes one of said first comparator ( 106 ) and said second comparator ( 110 ) to perform comparisons when the state is locked.    
     
     
         2 . The PLL device of  claim 1 , wherein said detector ( 118 ,  120 ,  122 ,  124 ) generates a lock detection signal from a pump-up signal and a pump-down signal output from the first comparator or the second comparator.  
     
     
         3 . A PLL device, comprising 
 a programmable frequency-division device ( 113 ,  114 ,  115 ,  116 ) that divides the frequency of the output of a voltage-controlled oscillator ( 112 );    a reference signal generating means ( 101 ,  102 ,  103 ,  104 ) generating a first reference signal and a second reference signal that differ in phase;    a first comparator ( 106 ) that compares the phases of said first reference signal and the output of said programmable frequency-division device;    a second comparator ( 110 ) that compares the phases of said second reference signal and the output of said programmable frequency-division device; and    a control unit ( 117 ); wherein    when the control unit ( 117 ) alters the frequency-division ratio from a first value to a second value, it selects a predetermined one of said first comparator ( 106 ) and said second comparator ( 110 ) according to the difference between said first value and said second value, and causes that comparator to perform the comparison.    
     
     
         4 . The PLL device of  claim 1  or  claim 3 , wherein said reference signal generating means ( 101 ,  102 ,  103 ,  104 ) generates said first reference signal (FR 11 ) and a plurality of second reference signals (FR 12 , FR 13 , FR 14 ) having different phases, and said second comparator ( 110 ) comprises a plurality of phase detectors ( 106 ,  107 ,  108 ,  109 ) that respectively compare the phases of said second reference signals and the output of said programmable frequency-division device.  
     
     
         5 . A PLL device, comprising: 
 a reference signal generating means ( 133 ,  134 ,  135 ,  136 ,  137 ) generating a plurality of reference signals with different phases;    programmable dividers ( 145 ,  146 ,  147 ,  148 ) receiving, through a first fixed divider ( 143 ), the output of a voltage-controlled oscillator ( 144 ), and dividing the frequency thereof; and    phase detectors ( 139 ,  140 ,  141 ,  142 ) comparing the phases of the outputs of said programmable dividers ( 145 ,  146 ,  147 ,  148 ) and said reference signals; wherein    a plurality of said programmable dividers ( 145 ,  146 ,  147 ,  148 ) are provided, each performing frequency division with a frequency-division ratio of the form A+B/C (where A, B, and C are integers, and B<C).    
     
     
         6 . The PLL device of  claim 5 , wherein said B is 1 and C is 2.  
     
     
         7 . The PLL device of  claim 6 , further comprising a second fixed divider dividing the reference frequency with a frequency-division ratio 2 n−1  (where n is an integer equal to or greater than two), wherein the frequency-division ratio of said first fixed divider is set to 2 n , and there are 2 n−1  of said programmable dividers.  
     
     
         8 . A PLL device, comprising: 
 a plurality of PLL circuits ( 202 ,  205 ), each having at least a first phase detector ( 204 ,  254 ) and a first programmable divider ( 205 ,  255 );    a driving unit ( 216 ) having at least one second phase detector ( 220 ,  221 ,  222 ) and at least one second programmable divider ( 223 ,  224 ,  225 ); and    a selective coupling means ( 235 ) selecting one PLL circuit ( 202 ,  252 ) from among said plurality of PLL circuits and coupling it to said driving unit ( 216 ).    
     
     
         9 . The PLL device of  claim 8 , wherein the first reference signal (FR 21 , FR 25 ) input to said first phase detector in said coupled PLL circuit differs in phase from the second reference signal (FR 22 , FR 23 , FR 24 ), which is input to said second phase detector.  
     
     
         10 . The PLL device of  claim 9 , wherein said selective coupling means ( 235 ) comprises: 
 a first selection switch ( 231 ) selecting one of the reference signals output from said plurality of PLL circuits and supplying it to said driving unit ( 216 );    a second selection switch ( 231 ) selecting one of the oscillator outputs of voltage-controlled oscillators in said plurality of PLL circuits and supplying it to said driving unit; and    a third selection switch ( 233 ) selectively supplying the output of the phase detector in said driving unit to (LPFs) in said plurality of PLL circuits.    
     
     
         11 . The PLL device of  claim 8 , wherein said plurality of PLL circuits ( 202 ,  252 ,  216 ) are allowed to output simultaneously to loads, and the one of said PLL circuits having a high set frequency is selected and coupled to said driving unit.  
     
     
         12 . A PLL device, comprising: 
 a generating means ( 306 ) that generates a plurality of reference signals with different phases;    a plurality of programmable dividers ( 311  to  314 ) that divide the frequency of the output of a voltage-controlled oscillator ( 315 ) and output feedback signals;    a plurality of phase detectors ( 307  to  310 ) that compare the phases of said reference signals and said feedback signals; and    a control unit ( 330 ) that starts the frequency division operations of said programmable dividers in synchronism with the phases of said reference signals.    
     
     
         13 . The PLL device of  claim 12 , further comprising switching elements ( 322  to  325 ) disposed between said voltage-controlled oscillator ( 315 ) and respective programmable dividers ( 311  to  314 ), wherein a gate control circuit ( 331 ) formed from logic circuits is provided in said control unit ( 330 ), and said gate control circuit ( 331 ) turns said switching elements on in synchronism with the phases of said reference signals.  
     
     
         14 . The PLL device of  claim 12 , wherein said control unit causes said frequency division operations to begin when a frequency alteration command or a lock failure signal is input.  
     
     
         15 . The PLL device of  claim 12 , wherein said control unit resets said programmable dividers before starting said frequency division operations.  
     
     
         16 . The PLL device of  claim 12 , wherein when said control unit detects lock, it causes a particular one of said programmable dividers to continue frequency division operation, and causes the other ones of said programmable dividers to stop frequency division operations.  
     
     
         17 . The PLL device of  claim 12 , wherein when said control unit detects lock, it causes the one of said programmable dividers on which the lock detection was performed to continue frequency division operation, and causes the other ones of said programmable dividers to stop frequency division operations.  
     
     
         18 . A PLL device, comprising: 
 a generating means ( 430 ) that generates a plurality of reference signals with different phases;    a main divider ( 430 ) that divides the frequency of the output signal of a voltage-controlled oscillator ( 429 ) by a frequency-division ratio N 1 ;    an auxiliary divider ( 431 ) that divides the frequency of the output of said main divider ( 430 ) by a frequency-division ratio N 2 ;    a distribution circuit ( 432 ) that distributes the output of said auxiliary divider ( 431 ) to a plurality of feedback signals; and    phase detectors ( 412  to  419 ) that compare said reference signals and said feedback signals, and output error signals; wherein    said main divider and said auxiliary divider each have a programmable divider or a counter.    
     
     
         19 . The PLL device of  claim 18 , adapted to make the product of said frequency-division ratio N 1  and said frequency-division ratio N 2  match a set frequency-division ratio of said output signal.  
     
     
         20 . The PLL device of  claim 18 , adapted to determine the value of said frequency-division ratio N 2  of said auxiliary divider in response to the size of said set frequency-division ratio.  
     
     
         21 . The PLL device of  claim 18 , comprising a plurality of phase detectors that compare said reference signals and said feedback signals, said frequency-division ratio N 2  being equal to or less than the number of said phase detectors.  
     
     
         22 . The PLL device of  claim 18 , adapted to have said main divider and said auxiliary divider divide the frequency of said output signal, then afterward to have only said main divider divide the frequency, for a certain set frequency-division ratio applying to said output signal.  
     
     
         23 . A PLL device, comprising: 
 a generating means ( 403 ) that generates a plurality of reference signals with different phases;    a first frequency-division unit ( 430 ,  431 ) and a second frequency-division unit ( 481 ), each dividing the frequency of the output signal of a voltage-controlled oscillator ( 429 ); and    phase detectors ( 412  to  419 ) that compare the phases of feedback signals output by said first frequency-division unit and said second frequency-division unit and said reference signals, and output error signals.    
     
     
         24 . The PLL device of  claim 23 , wherein said first frequency-division unit ( 430 + 431 ) comprises: 
 a main divider ( 430 ) that divides the frequency of said output signal by a frequency-division ratio N 1 ;    an auxiliary divider ( 431 ) that divides the frequency of the output of said main divider ( 430 ) by a frequency-division ratio N 2 ; and    a distribution circuit ( 482 ) that distributes the output of said auxiliary divider ( 431 ) to a plurality of said feedback signals;    said main divider ( 430 ) and said auxiliary divider ( 431 ) having programmable dividers or counters.    
     
     
         25 . The PLL device of  claim 24 , wherein said second frequency-division unit ( 481 ) comprises a programmable divider that performs frequency division with a set frequency-division ratio N, the PLL device being adapted to match the product of said frequency-division ratio N 1  and said frequency-division ratio N 2  to said set frequency-division ratio N or to a value close thereto.  
     
     
         26 . The PLL device of  claim 25 , adapted to operate said first frequency-division unit before lock, and to stop said first frequency-division unit after lock, 
 further adapted to cause said second frequency-division unit to perform frequency division with a frequency-division ratio equal to the product of said set frequency-division ratios N 1  and N 2  before lock, then after lock, to cause said second frequency-division unit to perform frequency division with said set frequency-division ratio N.    
     
     
         27 . The PLL device of  claim 23 , wherein said distribution circuit ( 482 ) outputs said feedback signals in synchronism with the timing of the generation of said reference signals, comprising a plurality of phase detectors that compare the phases of said feedback signals and said reference signals.  
     
     
         28 . A programmable frequency-division device, comprising: 
 a programmable divider ( 502 ,  542 ) that divides the frequency of an input signal alternately by N (where N is an integer) and by N+1;    a first output means ( 506 ,  546 ) that outputs a signal synchronized with the output of said programmable divider ( 502 ,  542 );    a second output means ( 509 ,  549 ) that outputs a signal in which a signal synchronized with the output of said programmable divider is delayed by one-half cycle with respect to said input signal;    a selection circuit ( 510 ,  550 ) that selects the output of said first output means when said programmable divider performs frequency division by N, and selects the output of said second output means when said programmable divider performs frequency division by N+1; and    a prevention means ( 507 ,  509 ;  534 ,  535 ) that prevents the output signal of said second output means from being delayed by more than said one-half cycle.    
     
     
         29 . The programmable divider of  claim 28 , wherein said first output means ( 506 ) has an input inverting function, said second output means does not have an input inverting function, and the first output means ( 506 ) and the second output means ( 509 ) constitute the prevention means.  
     
     
         30 . The programmable divider of  claim 28 , wherein said first output means ( 506 ) does not have an input inverting function, said second output means has an input inverting function, and the first output means ( 506 ) and the second output means ( 509 ) constitute the prevention means.  
     
     
         31 . The programmable divider of  claim 28 , wherein said prevention means comprises a first inverter ( 534 ) disposed between said first output means ( 546 ) and said selection circuit ( 550 ), and a second inverter ( 535 ) disposed between said input signal (B 1 ) and said second output means ( 549 ).