Circuit and method for impedance matching

Abstract

An impedance matching circuit ( 10 ) matches the impedance of a load ( 19 ) coupled to an RF amplifier ( 12 ) to that of the RF amplifier ( 12 ). The impedance matching circuit ( 10 ) samples a transmitted signal from the RF amplifier ( 12 ) and a reflected signal from the load ( 19 ). The amplitude and the phase of the sampled reflected signal are compared with those of the sampled transmitted signal to calculate the impedance mismatch. A control logic circuit ( 80 ) adjusts the capacitance and inductance values of variable capacitance ( 23, 27 ) and inductance ( 35 ) elements in the impedance matching circuit ( 10 ), thereby matching the impedance of the load ( 19 ) to that of the RF amplifier ( 12 ).

16 . A method for impedance matching, comprising the steps of: 
 sampling a first signal transmitted from a first circuit element to a second circuit element;    sampling a second signal reflected from the second circuit element in response to the first signal;    generating a first control signal in accordance with an amplitude of the first signal and an amplitude of the second signal;    generating a second control signal in accordance with a phase of the first signal and a phase of the second signal; and    adjusting an interface network in accordance with the first control signal and the second control signal.    
     
     
         17 . The method as claimed in claim  16 , wherein: 
 the step of sampling a first signal includes generating a first sampled signal;    the step of sampling a second signal includes generating a second sampled signal;    the step of generating a first control signal includes generating the first control signal based on a ratio of an amplitude of the first sampled signal to an amplitude of the second sampled signal; and    the step of generating a second control signal includes generating the second control signal based on a difference between a phase of the first sampled signal and a phase of the second sampled signal.    
     
     
         18 . The method as claimed in claim  16 , wherein the step of adjusting the interface network includes matching an input impedance of the second circuit element to an output impedance of the first circuit element.  
     
     
         19 . The method as claimed in claim  16 , wherein the step of adjusting the interface network includes the steps of: 
 generating a plurality of voltage signals in accordance with the first control signal and the second control signal; and    applying the plurality of voltage signals to the interface network.    
     
     
         20 . The method as claimed in claim  19 , wherein the step of adjusting the interface network further includes the steps of: 
 using a first voltage signal of the plurality of voltage signals to adjust a capacitance of a first shunt capacitor in the interface network, the first shunt capacitor being coupled between the first circuit element and a reference voltage;    using a second voltage signal of the plurality of voltage signals to adjust a capacitance of a second shunt capacitor in the interface network, the second shunt capacitor being coupled between the second circuit element and the reference voltage; and    using a third voltage signal of the plurality of voltage signals to adjust a capacitance of a series capacitor in the interface network, the series capacitor being coupled in series with an inductor between the first circuit element and the second circuit element.