Method of reducing junction spiking through a wall surface of an overetched contact via

Abstract

The present invention pertains to a semiconductor device microstructure, and to a method of forming that microstructure, which reduces or prevents junction spiking and to a method of forming that microstructure. In particular, a semiconductor contact microstructure comprises a feature which includes a silicon base and at least one sidewall extending upward from the silicon base. The sidewall includes a silicon portion in contact with the silicon base, where the height of the silicon portion of the sidewall above the silicon base is typically less than about 0.5 μm. The sidewall also includes at least one portion which comprises a first dielectric material which is in contact with (and typically extends upward from) the silicon portion of the sidewall. Overlying at least the silicon portion of the sidewall is a layer of a second dielectric material, preferably silicon oxide. Typically, a diffusion barrier layer overlies the silicon base, the layer of second dielectric material, and at least part of the sidewall portion which is comprised of the first dielectric material. The method comprises the steps of: a) providing a semiconductor device feature which includes a silicon base and at least one sidewall extending upward from the silicon base, where the sidewall includes at least one silicon portion in contact with the silicon base, and another portion comprising a first dielectric material which is in contact with the silicon portion of the sidewall; and b) creating a layer of a second dielectric material, preferably silicon oxide, over the at least one silicon sidewall portion. The method may include additional steps: c) sputter etching to remove dielectric material from the surface of the silicon base; and d) applying a diffusion barrier material over the silicon base, the layer of second dielectric material, and at least a portion of the sidewall comprising the first dielectric material. Typically, both the first and second dielectric materials are silicon oxide.

We claim:  
     
         1 . A semiconductor contact microstructure which reduces junction spiking, said microstructure comprising a feature which includes a silicon base, at least one silicon sidewall portion in contact with and extending upward from said silicon base, and at least one sidewall portion comprising a first dielectric material which is in contact with said silicon sidewall portion, wherein, overlying at least the silicon portion of said sidewall is a layer of a second dielectric material.  
     
     
         2 . The semiconductor contact microstructure of  claim 1 , further including a diffusion barrier layer overlying said silicon base, said second dielectric layer, and at least a portion of said first dielectric sidewall material.  
     
     
         3 . The semiconductor contact microstructure of  claim 1  or  claim 2 , wherein the height of said silicon sidewall portion extending upward from said silicon base is less than about 0.5 μm.  
     
     
         4 . The microstructure of  claim 1  or  claim 2 , wherein said second dielectric material is selected from the group consisting of silicon oxide, silicon nitride, PSG, and BPSG.  
     
     
         5 . The microstructure of  claim 4 , wherein said second dielectric material is silicon oxide.  
     
     
         6 . The microstructure of  claim 5 , wherein said second dielectric material is thermally generated silicon oxide.  
     
     
         7 . The microstructure of  claim 1  or  claim 2 , wherein the thickness of said layer of second dielectric material overlying said silicon portion of said sidewall is within the range of about 50 Å to about 100 Å.  
     
     
         8 . The microstructure of  claim 2 , wherein said diffusion barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof.  
     
     
         9 . A method of reducing or preventing junction spiking in a contact via formed in a silicon substrate, the method comprising the following steps: 
 a) providing a semiconductor device feature which includes a silicon base and at least one sidewall extending upward from said silicon base, where said sidewall includes at least one silicon portion in contact with said silicon base and another portion comprising a first dielectric material which is in contact with said silicon portion of said sidewall; and    b) creating a layer of a second dielectric material over said at least one silicon portion of said sidewall.    
     
     
         10 . The method of  claim 9 , including the additional steps: 
 c) sputter etching to remove dielectric material from a surface of said silicon base; and    d) applying a diffusion barrier layer over said silicon base, said second dielectric layer overlying said silicon portion of said sidewall, and at least a portion of said sidewall comprising a first dielectric material.    
     
     
         11 . The method of  claim 9  or  claim 10 , wherein the height of said silicon sidewall portion extending upward from said silicon base is less than about 0.5 μm.  
     
     
         12 . The method of  claim 11 , wherein said second dielectric material is selected from the group consisting of silicon oxide, silicon nitride, PSG, and BPSG.  
     
     
         13 . The method of  claim 12 , wherein said second dielectric material is silicon oxide.  
     
     
         14 . The method of  claim 13 , wherein said silicon oxide is formed by thermal oxidation.  
     
     
         15 . The method of  claim 12 , wherein said layer of second dielectric material is deposited using chemical vapor deposition.  
     
     
         16 . The method of  claim 9  or  claim 10 , wherein said layer of second dielectric material is formed to have a thickness within the range of about 50 Å to about 100 Å.  
     
     
         17 . The method of  claim 10 , wherein said diffusion barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof.  
     
     
         18 . The method of  claim 17 , wherein said diffusion barrier layer is deposited by physical vapor deposition.  
     
     
         19 . The method of  claim 18 , wherein said diffusion barrier layer is deposited by high density plasma sputter deposition.  
     
     
         20 . The method of  claim 10 , wherein the method further comprises the following step: 
 e) applying a metallic conductor over said diffusion barrier layer.    
     
     
         21 . The method of  claim 20 , wherein said metallic conductor is aluminum, and said diffusion barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, and combinations thereof.  
     
     
         22 . The method of  claim 20 , wherein said metallic conductor is copper, and said diffusion barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, and combinations thereof.