Image processor circuits, systems, and methods

Abstract

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

What is claimed is:  
     
         1 . A processing system for an imager device comprising: 
 a camera system for producing an imager signal;    a correlated double sample (CDS) circuit for receiving data from an imager;    a variable gain amplifier (VGA);    an analog-to-digital converter (ADC) coupled to said CDS circuit;    a digital gain circuit (DGC) coupled to said ADC; and    an automatic gain control (AGC) circuit coupled to said DGC, effective for controlling said CDS circuit and said DGC.    
     
     
         2 . A processing system according to  claim 1  comprising a black level circuit.  
     
     
         3 . A processing system according to  claim 1  comprising a programmable timing generator.  
     
     
         4 . A processing system according to  claim 1 , wherein said AGC is effective for controlling the gain of said camera system.  
     
     
         5 . A processing system according to  claim 4 , wherein said AGC is effective for controlling said timing circuit.  
     
     
         6 . A processing system according to  claim 5 , wherein said timing circuit controls gain.  
     
     
         7 . The processing system according to  claim 1  including a read only memory (ROM) and a multiplier effective for multiplying an ADC output with a selected copy multiplicand from said ROM.  
     
     
         8 . A correlated double sampler and variable gain amplifier (CDSVGA) circuit for receiving CCD data, comprising: 
 a first fixed capacitor for receiving CCD data;    a first amplifier connected to said first fixed capacitor for amplifying CCD data, said first amplifier connected to said first fixed capacitor;    a first variable capacitor connected in parallel with said first amplifier;    a first switch connect in parallel with said first variable capacitor, said first switch being clocked at a first clock phase;    a second variable capacitor connected to said first amplifier;    a second amplifier connected to said second variable amplifier;    a second fixed capacitor connected in parallel with said second amplifier; and    a second switch connected in parallel with said second fixed amplifier; said second switch being clocked at a second clock phase.    
     
     
         9 . A distributed gain control circuit (DGCC) comprising: 
 an imager signal source;    a timing circuit for controlling the production of signals to said imager signal source;    an amplifier system for receiving imager signals from said imager signal source;    an analog to digital converter connected to said amplifier for receiving an amplified imager signal stream from said amplifier and converting the amplified imager signal stream into digital form;    a digital gain circuit connected to said analog to digital converter; and    an automatic gain control (AGC) circuit for receiving an output digital level from said digital gain circuit for controlling the gain of said amplifier system and said digital gain circuit subject to a predetermined gain function (PGF).    
     
     
         10 . The DGCC according to  claim 9  wherein said AGC circuit is coupled to said timing circuit for controlling the production of signals to said imager signal source.  
     
     
         11 . The DGCC according to  claim 9  wherein said PGF increases gain first with said amplifier and then with said digital gain circuit.  
     
     
         12 . The DGCC according to  claim 9  wherein said PGF decreases gain first with said digital gain circuit and then said amplifier.  
     
     
         13 . The DGCC according to  claim 9  including a formatter circuit for restructuring the output digital format of the DGCC.  
     
     
         14 . The DGCC according to  claim 9  wherein the restructuring includes adding end-of-video and start-of-video signal codes to the output signal stream.  
     
     
         15 . A signal processing system (SPS) on an integrated substrate for a video camera comprising: 
 analog front-end (AFE) circuitry, and digital signal processing system (DSPS) circuitry connected to the analog front-end (AFE) circuitry.    
     
     
         16 . The SPS according to  claim 15  wherein said SPS performs signal processing for a CCD camera capable of capturing full motion video.  
     
     
         17 . The SPS according to  claim 15  comprising a digital video camera including a CCD array, a high voltage CCD driver, and a DC-DC converter.  
     
     
         18 . The SPS according to  claim 15  wherein said AFE receives a mosaic CCD output from a CCD camera.  
     
     
         19 . The SPS according to  claim 15  wherein said DSPS accepts a digital output of the AFE, performs digital processing on the received digital output of the AFE, and outputs a CCIR 601 like 4:2:2 YCrCb video data product.  
     
     
         20 . The SPS according to  claim 15  comprising a plurality of registers configured to share the address spaces of both the AFE and the DSPS, whereby to an external controller, the AFE, and the DSPS appear as a single device.  
     
     
         21 . The SPS according to  claim 15  wherein said AFE and said DSPS can be used as stand-alone systems which is addressed directly through respective I2C interfaces.  
     
     
         22 . The SPS according to  claim 15  wherein said AFE and DSPS are fabricated on separate semiconductor substrates to enable the installation of the AFE and its analog functions with a CCD camera package jointly with a CCD imager.  
     
     
         23 . The SPS according to  claim 15  wherein digital data processing can be selectably accomplished within a predetermined camera package or in a selected computer.  
     
     
         24 . The SPS according to  claim 15  wherein said DSPS and said AFE respectively comprise digital and analog signal processing functions which are adaptively localizable and delocalizable.  
     
     
         25 . The SPS according to  claim 15  wherein said AFE and said DSPS are respective selectably distributable analog and digital functionalities, enabling CCD signal processing to be localized for silicon fabrication.  
     
     
         26 . The SPS according to  claim 15  wherein said AFE is fabricated in silicon and said DSPS is software implemented.  
     
     
         27 . The SPS according to  claim 15  wherein said AFE and said DSPS are operable at different data rates.  
     
     
         28 . The SPS according to  claim 15  wherein said AFE is scalable for a plurality of selected CCD output formats and pixel rates.  
     
     
         29 . The SPS according to  claim 15  comprising horizontal and vertical shift register clocks, CCD output sampling pulse circuits and circuitry for specifying the number of horizontal and vertical pixels per frame, which are programmable.