Electronic power device integrated on a semiconductor material and related manufacturing process

Abstract

An electronic power device is integrated on a semiconductor substrate having a first conductivity type, on which an epitaxial layer of the same conductivity type is grown. The power device comprises a power stage and a control stage, this latter enclosed in an isolated region having a second conductivity type. The power stage comprises a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area and having the first conductivity type. The control stage comprises a third buried area, having the second conductivity type, and a fourth buried area, partially overlapped to the third buried area and having the first conductivity type. Said first, second, third and fourth buried areas are formed in the epitaxial layers at a depth sufficient to allow the power stage and the control stage to be entirely formed in the epitaxial layer.

1 . An electronic power device integrated on a substrate of semiconductor material having a first conductivity type, on which an epitaxial layer, of the first conductivity type, is grown, said power device comprising: a power stage PT and a control stage CT, the latter enclosed in an isolation region having a second conductivity type, said power stage PT comprising a first buried area having the second conductivity type and a second buried area, partially overlapping the first buried area, and having the first conductivity type, said isolation region and said control stage CT comprising respectively a third buried area, having a second conductivity type, and a fourth buried area, partially overlapping the third buried area and having a first conductivity type, wherein said first, second third and fourth buried areas are formed in the epitaxial layer at a depth sufficient to allow the power stage PT and the control stage CT to be entirely formed in the epitaxial layer.  
     
     
         2 . The power device according to  claim 1 , wherein said first and third buried areas are placed at a depth of about 6 μm from an upper surface of the epitaxial layer.  
     
     
         3 . The power device according to  claim 2 , wherein said second and fourth buried areas are placed at a depth of about 3-4 μm from the upper surface of the epitaxial layer.  
     
     
         4 . The power device of  claim 1 , further comprising: 
 first, second, third, and fourth contact regions positioned in the epitaxial layer, the first and second contact regions extending from a surface of the epitaxial layer to contact opposite ends of the first buried area, and the third and fourth contact regions extending from the surface of the epitaxial layer to contact opposite ends of the third buried area.    
     
     
         5 . The power device of  claim 4  wherein the second buried area is positioned between the first and second contact regions and the fourth buried area is positioned between the third and fourth contact regions.  
     
     
         6 . The power device of  claim 1 , further comprising first and second contact regions extending from a surface of the epitaxial region to contact opposite ends of the fourth buried region.  
     
     
         7 . The power device of  claim 6 , further comprising a doped region of the second conductivity type positioned in the epitaxial layer and between the first and second contact regions.  
     
     
         8 . The power device of  claim 7 , further comprising a doped region of the first conductivity type positioned in the doped region of the second conductivity type.  
     
     
         9 . The power device of  claim 1 , wherein the power stage PT includes: 
 a surface contact region of the first conductivity type positioned in the epitaxial layer, wherein the second buried area is formed below and in contact with the surface contact region, thereby forming a vertical transistor in which the surface contact region and second buried area together form an emitter, the first buried area forms a base, and the epitaxial layer forms a collector.    
     
     
         10 . The electronic power device of  claim 1  wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.  
     
     
         11 . The electronic power device of  claim 10  wherein the third and fourth buried layers are annular.  
     
     
         12 . An electronic power device integrated on a semiconductor substrate, comprising: 
 an epitaxial layer formed on the semiconductor substrate;    first and second buried layers formed in the epitaxial layer at a first level, the first buried layer forming an isolation region for a control transistor and the second buried layer forming a control region of a power transistor;    third and fourth buried layers formed in the epitaxial layer at a second level, the third and fourth buried layers partially overlapping the first and second buried layers, respectively, the third buried layer forming a first conduction region of the control transistor and the fourth buried layer forming a conduction region of the power transistor; and    first and second surface contact regions formed in the epitaxial layer, the first surface contact region forming a control region of the control transistor and the second surface contact region forming a second conduction region of the control transistor.    
     
     
         13 . The electronic power device of  claim 12  wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.  
     
     
         14 . The electronic power device of  claim 13  wherein the third and fourth buried layers are annular.  
     
     
         15 . The electronic power device of  claim 12  wherein the control transistor includes a vertical signal transistor and a lateral signal transistor.  
     
     
         16 . The electronic power device of  claim 15  wherein the third buried layer forms a first conduction region of the vertical signal transistor and a control region of the lateral signal transistor, the first contact region forms a control region of the vertical signal transistor and first and second conduction regions of the lateral signal transistor, and the second contact region forms a second conduction region of the vertical signal transistor.  
     
     
         17 . The electronic power device of  claim 12  wherein the first and second buried regions are formed at a depth of about 6 mm from an upper surface of the epitaxial layer and the third and fourth buried regions are formed at a depth of about 3-4 mm from the upper surface of the epitaxial layer.  
     
     
         18 . An electronic power device integrated on a semiconductor substrate, comprising: 
 an epitaxial layer formed on the semiconductor substrate;    first and second buried layers formed in the epitaxial layer at a first level, the first buried layer forming an isolation region for a control transistor and the second buried layer forming a control region of a power transistor;    third and fourth buried layers formed in the epitaxial layer at a second level, the third and fourth buried layers partially overlapping the first and second buried layers, respectively, the third buried layer forming a first conduction region of the control transistor and the fourth buried layer forming a conduction region of the power transistor; and    a surface contact region positioned in the epitaxial layer, wherein the second buried area is formed below and in contact with the surface contact region, thereby forming a vertical transistor in which the surface contact region and second buried area together form an emitter, the first buried area forms a base, and the epitaxial layer forms a collector.    
     
     
         19 . The power device of  claim 18 , wherein said first and third buried areas are placed at a depth of about 6 μm from an upper surface of the epitaxial layer and said second and fourth buried areas are placed at a depth of about 3-4 μm from the upper surface of the epitaxial layer.  
     
     
         20 . The power device of  claim 18 , further comprising: 
 first, second, third, and fourth contact regions positioned in the epitaxial layer, the first and second contact regions extending from a surface of the epitaxial layer to contact opposite ends of the first buried area, and the third and fourth contact regions extending from the surface of the epitaxial layer to contact opposite ends of the third buried area.    
     
     
         21 . The power device of  claim 20  wherein the second buried area is positioned between the first and second contact regions and the fourth buried area is positioned between the third and fourth contact regions.  
     
     
         22 . The power device of  claim 18 , further comprising first and second contact regions extending from a surface of the epitaxial region to contact opposite ends of the fourth buried region.  
     
     
         23 . The power device of  claim 22 , further comprising a doped region of the second conductivity type positioned in the epitaxial layer and between the first and second contact regions.  
     
     
         24 . The power device of  claim 23 , further comprising a doped region of the first conductivity type positioned in the doped region of the second conductivity type.  
     
     
         25 . The electronic power device of  claim 18  wherein the first and second buried layers are annular and the third and fourth buried layers are formed in the annular first and second buried layers, respectively.  
     
     
         26 . The electronic power device of  claim 25  wherein the third and fourth buried layers are annular.