Image conversion device, image conversion method and data conversion circuit as well as digital camera

Abstract

An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.

What is claimed is:  
     
         1 . An image conversion device, which converts image data from dot sequential data to color field sequential data, comprising: 
 an image storing unit which has a first buffer area for storing either one of odd and even fields and a second buffer area for storing the other field of said odd and even fields, said odd field consisting of odd-numbered lines of said dot sequential data, said even field consisting of even-numbered lines of said dot sequential data; and    a data transfer control circuit which carries out such controlling operations that, during a period in which said dot sequential data are written in one of said first and second buffer areas, pixel data of said even field or said odd field stored in the other buffer area are read out in a color field sequential format.    
     
     
         2 . The image conversion device according to  claim 1 , further comprising: 
 a pixel interpolating circuit which generates and outputs pixel interpolation data formed by carrying out an interpolating process between respective lines of color field sequential data read from said buffer area.    
     
     
         3 . The image conversion device according to  claim 1 , further comprising: 
 a color-space conversion circuit for color-space converting said dot sequential data; and    a sub-sampling circuit for sub-sampling dot sequential data outputted from said color-space conversion circuit to output the resulting data to said image storing unit.    
     
     
         4 . The image conversion device according to  claim 1 , further comprising: 
 an over-sampling circuit for over-sampling color field sequential data read from said image storing unit; and    a second color space conversion circuit for carrying out color-space conversion on color field sequential data outputted from said over-sampling circuit.    
     
     
         5 . The image conversion device according to  claim 1 , further comprising: 
 an intra-frame determining circuit which makes a determination as to whether or not dot sequential data to be inputted to said image storing unit are coincident with dot sequential data stored in said image storing unit on a frame basis; and    an operation mode control circuit which controls said data transfer control circuit based upon the results of determination of said intra-frame determination circuit,    wherein under control of said operation mode control circuit,    when said intra-frame determining circuit has made a determination as non-coincidence, said data transfer control circuit proceeds to a motion image display mode to carry out such a controlling operation that, during a period in which said odd field or said even field is written in one of said first and second buffer areas, said even field or said odd field stored in the other buffer area is read out in a color field sequential format, and    when said intra-frame determining circuit has made a determination as coincidence, said data transfer control circuit proceeds to a still image display mode to carry out such a controlling operation that said even field and said odd field stored in said first and second buffer areas are read out in a color field sequential format on a frame basis.    
     
     
         6 . An image conversion method, which converts image data from dot sequential data to color field sequential data, comprising the steps of: 
 (a) alternately storing an odd field consisting of odd numbered lines of said dot sequential data and an even field consisting of even numbered lines of said dot sequential data respectively in first and second buffer areas; and    (b) during a period in which said odd field or said even field is written in one of said buffer areas in said process (a), reading pixel data of said even field or said odd field stored in the other buffer area in a color field sequential format.    
     
     
         7 . The image conversion method according to  claim 6 , further comprising the step of: 
 (c) generating and outputting pixel interpolating data formed by carrying out an interpolating process on color field sequential data read from said buffer area in said step (b).    
     
     
         8 . The image conversion method according to  claim 6 , wherein said step (a) comprises the step of: 
 (a-1) color-space converting said dot sequential data to sub-sample and store the resulting data in said buffer areas.    
     
     
         9 . The image conversion method according to  claim 6 , wherein said step (c) comprises the step of: 
 (c-1) over-sampling the image data read from said buffer area to color-space convert the resulting data.    
     
     
         10 . The image conversion method according to  claim 6 , wherein said step (a) further comprises the steps of: 
 (a-2) making a determination as to whether or not said dot sequential data to be inputted are coincident with dot sequential data stored in said buffer area on a frame basis;    (a-3) upon determination as non-coincidence at said step (a- 2 ), proceeding to a motion image display mode for executing said step (b); and    (a-4) upon determination as coincidence at said step (a- 2 ), proceeding to a still image display mode in which said even field and said odd field stored in said first and second buffer areas are read out in color field sequential format on a frame basis.    
     
     
         11 . A data conversion circuit, which converts a color component array of image data to a color field sequential format, comprising: 
 first buffer memory and second buffer memory that alternately store on a frame basis or on a field basis pixel data having a single color component in each pixel;    control means which carries out such controlling operations that, during a period in which said pixel data are stored in one of said first buffer memory and said second buffer memory, said pixel data stored in the other are selectively read and outputted; and    an interpolating unit which, using pixel data in a specific area outputted from said first buffer memory and said second buffer memory by said control means, executes a pixel interpolating process to generate interpolated data having a plurality of color components in each pixel, and outputs said interpolated data to a color field sequential display in a field sequential color-component array.    
     
     
         12 . The data conversion circuit according to  claim 11 , further comprising: 
 a resolution conversion unit which resolution-converts said image data so as to fit to capacity of said first buffer memory and said second buffer memory, and then outputs the resulting data to said first buffer memory and said second buffer memory.    
     
     
         13 . The data conversion circuit according to  claim 11 , further comprising: 
 a signal conversion circuit which receives dot sequential data having a plurality of color components in each pixel as input data, and converts the dot sequential data to pixel data having a single color component in each pixel.    
     
     
         14 . The data conversion circuit according to  claim 13 , further comprising: 
 a selector which selects either of pixel data having a single color component in each pixel and pixel data of said dot sequential data as converted and outputted by said signal conversion circuit, to output the resulting data to said first buffer memory and said second buffer memory.    
     
     
         15 . The data conversion circuit according to  claim 13 , further comprising: 
 a second selector which selects either of said dot sequential data having a plurality of color components in each pixel and pixel data of said dot sequential data as converted and outputted by said signal conversion circuit to output the resulting data to said first buffer memory and said second buffer memory, each of said first buffer memory and said second buffer memory having a capacity corresponding to at least a half of one frame of said dot sequential data,    wherein, when said second selector selects and outputs said dot sequential data, said control means carries out such controlling operations that, during a period in which either of an odd field consisting of odd numbered lines of said dot sequential data and an even field consisting of even numbered lines of said dot sequential data is stored in either of said first buffer memory and said second buffer memory, the other field stored in the other of said first buffer memory and said second buffer memory is read out, and    wherein said interpolating unit generates interpolated data formed by interpolating an insufficient field to said read-out odd field or even field, and outputs the resulting interpolated data to a color field sequential display in said field sequential color-component array.    
     
     
         16 . The data conversion circuit according to  claim 11 , wherein said interpolating unit comprises a color space conversion circuit for executing a color space converting operation by using a variable conversion coefficient.  
     
     
         17 . The data conversion circuit according to  claim 11 , wherein said interpolating unit comprises an on-screen display circuit for multiplexing said interpolated data, character information and graphic information.  
     
     
         18 . The data conversion circuit according to  claim 11 , further comprising a gamma correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for carrying out a gamma conversion process on inputted image data.  
     
     
         19 . The data conversion circuit according to  claim 11 , further comprising an OB correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for correcting a luminance level of said image data based upon a luminance level acquired from an OB (optical black) area of inputted image data.  
     
     
         20 . The data conversion circuit according to  claim 11 , further comprising a gain correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for adjusting gain of image data.  
     
     
         21 . The data conversion circuit according to  claim 11 , further comprising a WB correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for adjusting white balance of inputted image data.  
     
     
         22 . The data conversion circuit according to  claim 11 , further comprising an AF evaluation circuit provided at a stage prior to said first buffer memory and said second buffer memory for calculating an AF (auto-focus) evaluation value based upon inputted image data.  
     
     
         23 . A digital camera comprising: 
 an image-pickup sensor having a color-filter array of a single-chip type;    an A/D conversion circuit which generates and outputs raw image data having only a single color component in each pixel by A/D converting an image signal outputted from said image-pickup sensor;    an image processing unit which generates and outputs dot sequential data having a plurality of color components in each pixel by image-processing said raw image data;    a color field sequential display for displaying color field sequential data formed by arranging image data for each color component on a frame basis or on a field basis; and    a data conversion circuit which converts the color component array of image data to a color field sequential format, and outputs the resulting data to color field sequential display,    wherein said data conversion circuit comprises: 
 a first buffer memory and a second buffer memory that alternately store said raw image data on a frame basis or on a field basis;  
 control means which carries out such control operations that, during a period in which said raw image data are stored in one of said first buffer memory and said second buffer memory, pixel data stored in the other are selectively read and outputted; and  
 an interpolating unit which generates interpolated data having a plurality of color components in each pixel by carrying out a pixel interpolating process using pixel data in a specific area outputted from said first buffer memory and said second buffer memory by said control means, and outputs said interpolated data to said color field sequential display in a field sequential color component array.  
   
     
     
         24 . The digital camera according to  claim 23 , wherein said color field sequential display forms a view finder.  
     
     
         25 . The digital camera according to  claim 23 , wherein said data conversion circuit further comprises a resolution conversion unit which resolution-converts said raw image data so as to fit to capacity of said first buffer memory and said second buffer memory, and then outputs the resulting data to said first buffer memory and said second buffer memory.  
     
     
         26 . The digital camera according to  claim 23 , wherein 
 said data conversion circuit comprises a signal conversion circuit which receives dot sequential data having a plurality of color components in each pixel as input data, and converts the dot sequential data to data in a raw image format having a single color component in each pixel so as to output the resulting data; and    said control means carries out such controlling operations that said data in the raw image format are alternately stored in said first buffer memory and said second buffer memory on a frame basis or on a field basis, and so that, during a period in which said data in the raw image format are stored in one of said first buffer memory and said second buffer memory, pixel data stored in the other are selectively read and outputted.    
     
     
         27 . The digital camera according to  claim 26 , wherein said data conversion circuit comprises a selector which selects either of said raw image data and said data in the raw image format outputted from said signal conversion circuit to output the resulting data to said first buffer memory and said second buffer memory.  
     
     
         28 . The digital camera according to  claim 26 , wherein said data conversion circuit comprises a second selector which selects either of said dot sequential data having a plurality of color components in each pixel and said data in the raw image format outputted from said signal conversion circuit, and outputs the resulting data to said first buffer memory and said second buffer memory, each of said first buffer memory and said second buffer memory having a capacity corresponding to at least a half of one frame of said dot sequential data, 
 wherein, when said second selector selects and outputs said dot sequential data, said control means carries out such controlling operations that, during a period in which either of an odd field consisting of odd numbered lines of said dot sequential data and an even field consisting of even numbered lines of said dot sequential data is stored in either of said first buffer memory and said second buffer memory, the other field stored in the other of said first buffer memory and said second buffer memory is read out, and    wherein said interpolating unit generates interpolated data formed by interpolating an insufficient field to said read-out odd field or said even field, and outputs the interpolated data to a color field sequential display in said field sequential color-component array.    
     
     
         29 . The digital camera according to  claim 23 , wherein said interpolating unit comprises a color space conversion circuit for executing a color space converting operation by using a variable conversion coefficient.  
     
     
         30 . The digital camera according to  claim 23 , wherein said interpolating unit comprises an on-screen display circuit for multiplexing said interpolated data, character information and graphic information.  
     
     
         31 . The digital camera according to  claim 23 , wherein said data conversion circuit comprises a gamma correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for carrying out a gamma conversion process on inputted image data.  
     
     
         32 . The digital camera according to  claim 23 , wherein said data conversion circuit comprises an OB correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for correcting a luminance level of said image data based upon a luminance level acquired from an OB (optical black) area of inputted image data.  
     
     
         33 . The digital camera according to  claim 23 , wherein said data conversion circuit comprises a gain correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for adjusting gain of image data.  
     
     
         34 . The digital camera according to  claim 23 , wherein said data conversion circuit comprises a WB correction circuit provided at a stage prior to said first buffer memory and said second buffer memory for adjusting white balance of inputted image data.  
     
     
         35 . The digital camera according to  claim 23 , wherein said data conversion circuit comprises an AF evaluation circuit provided at a stage prior to said first buffer memory and said second buffer memory for calculating an AF (auto-focus) evaluation value based upon inputted image data.  
     
     
         36 . A data conversion circuit comprising: 
 a sampling unit for sampling input image data having a plurality of components per pixel to output image data having a single component in each pixel;    a key signal calculation unit for calculating a key signal having a value corresponding to a correlation state between a specific pixel of said input image data and surrounding pixels thereof;    writing control means which carries out such controlling operations that image data outputted from said sampling unit and said key signal are stored in a buffer memory on a frame basis or on a field basis;    reading control means which carries out such controlling operations that said image data and said key signal stored in said buffer memory are read out on a frame basis or on a field basis; and    an interpolating unit which carries out a pixel interpolating process for interpolating a plurality of components in each pixel to said image data read out by said reading control means in accordance with a value of said key signal to output interpolated data obtained by said pixel interpolating process to a display device.    
     
     
         37 . The data conversion circuit according to  claim 36 , wherein 
 said writing control means makes said buffer memory store combined data formed by combining said image data outputted from said sampling unit with said key signal, and    said interpolating unit carries out said pixel interpolating process on said image data obtained by separating said combined data read from said buffer memory by said reading control means.    
     
     
         38 . The data conversion circuit according to  claim 36 , wherein 
 said writing control means makes said buffer memory store data formed by including said key signal in low bit position of said image data outputted from said sampling unit in said buffer memory, and    said interpolating unit extracts said image data and said key signal from data read from said buffer memory by said reading control means, and executes said pixel interpolating process.    
     
     
         39 . The data conversion circuit according to  claim 36 , wherein 
 said buffer memory comprises a first buffer memory and a second buffer memory,    said writing control means carries out such controlling operations that said image data and said key signal are stored in said first buffer memory and said second buffer memory, alternately, on a frame basis or on a field basis,    said reading control means carries out such controlling operations that, during a period in which data are written in either one of said first buffer memory and said second buffer memory, data stored in the other memory are read out on a frame basis or on a field basis, and    said interpolating unit generates said interpolated data in a color field sequential format that are formed by arranging said respective components on a frame basis or on a field basis from said image data in a dot sequential format in which said respective components are arranged on a pixel basis.    
     
     
         40 . The data conversion circuit according to  claim 39 , wherein said interpolating unit generates said interpolated data in a color field sequential format at a frame rate different from a frame rate of said input image data.  
     
     
         41 . The data conversion circuit according to  claim 36 , wherein 
 said buffer memory comprises a first buffer memory and a second buffer memory,    said writing control means carries out such controlling operations that said image data and said key signal are stored in said first buffer memory and said second buffer memory, alternately, on a frame basis or on a field basis,    said reading control means carries out such controlling operations that, during a period in which data are written in either one of said first buffer memory and said second buffer memory, data stored in the other memory are read out on a frame basis or on a field basis, and    said interpolating unit carries out said pixel interpolating process at a frame rate different from a frame rate of said input image data to output said interpolated data.