Semiconductor memory device

Abstract

A switching transistor to connect a pair of bit lines in a sub array to a pair of common bit lines in a sense amplifier band is arranged between a P channel sense amplifier and an N channel sense amplifier. Accordingly, the switching transistor can be used of a threshold value identical to that of the NMOSFET used in a logic circuit region, not a low threshold value. Therefore, the switching transistor can be reliably turned on/off in a narrow operating range. Accordingly, the complexity or capability of the drive circuit can be suppressed to a low level. As a result, the area for the semiconductor memory device can be reduced.

What is claimed is:  
     
         1 . A semiconductor memory device comprising a first switching transistor for connecting a bit line extending from a memory sub array including a memory cell transistor to a first sense amplifier, said first switching transistor being arranged at a side opposite to said memory sub array than the input side of said sense amplifier.  
     
     
         2 . The semiconductor memory device according to  claim 1 , wherein said first sense amplifier includes a first P channel sense amplifier and an N channel sense amplifier, said first switching transistor being arranged between the first P channel sense amplifier and N channel sense amplifier to effect isolation and connection therebetween.  
     
     
         3 . The semiconductor memory device according to  claim 1 , wherein said memory cell transistor has a threshold value lower than the threshold value of said first switching transistor.  
     
     
         4 . The semiconductor memory device according to  claim 2 , further comprising a N channel drive transistor connected between a power supply node and said first P channel sense amplifier.  
     
     
         5 . A semiconductor memory device comprising: 
 a first common bit line,    a second common bit line complementary to said first common bit line,    an N channel sense amplifier connected between said first and second common bit lines,    a first bit line,    a second bit line complementary to said first bit line,    a first P channel sense amplifier connected between said first and second bit lines,    a first switching transistor connected between said first common bit line and said first bit line,    a second switching transistor connected between said second common bit line and said second bit line,    a third bit line,    a fourth bit line complementary to said third bit line,    a second P channel sense amplifier connected between said third and fourth bit lines,    a third switching transistor connected between said first common bit line and said third bit line,    a fourth switching transistor connected between said second common bit line and said fourth bit line,    a word line,    a memory cell capacitor, and    a memory cell transistor connected between said first bit line and said memory cell capacitor, having a gate connected to said word line.    
     
     
         6 . The semiconductor memory device according to  claim 5 , wherein said memory cell transistor has a threshold value lower than the threshold value of said first switching transistor.  
     
     
         7 . The semiconductor memory device according to  claim 5 , further comprising an N channel drive transistor connected between a power supply node and said first P channel sense amplifier.  
     
     
         8 . The semiconductor memory device according to  claim 7 , wherein said N channel drive transistor has a threshold value lower than the threshold value of said first switching transistor.  
     
     
         9 . The semiconductor memory device according to claim 7 , wherein said N channel drive transistor has a threshold value substantially equal to the threshold value of said memory cell transistor.  
     
     
         10 . The semiconductor memory device according to  claim 7 , further comprising a control circuit selectively applying a power supply voltage and a ground voltage to a gate of said N channel driver transistor.  
     
     
         11 . The semiconductor memory device according to  claim 5 , wherein each of said sense amplifiers comprises two sense transistors that are cross-coupled, wherein said sense transistor, said memory cell transistor and said switching transistor have gate insulating films of the same thickness.  
     
     
         12 . The semiconductor memory device according to  claim 5 , wherein said memory cell transistor has a back gate connected to ground.  
     
     
         13 . A semiconductor memory device comprising: 
 a semiconductor substrate,    a dynamic random access memory formed on said semiconductor substrate, and    a logic circuit formed on said semiconductor substrate to control said dynamic random access memory,    wherein a memory cell capacitor in said dynamic random access memory has a capacitor insulating film of a thickness substantially equal to the thickness of a gate insulating film of a transistor that forms said logic circuit.    
     
     
         14 . The semiconductor memory device according to  claim 13 , wherein said memory cell capacitor includes a cell plate electrode connected to ground.  
     
     
         15 . A semiconductor memory device comprising: 
 a power supply line,    a ground line, and    a plurality of memory cell arrays, wherein each of said memory cell array comprises 
 a sub array including a plurality of bit line pairs, and  
 a sense amplifier band adjacent to said sub array,  
 wherein said sense amplifier band comprises 
 a plurality of P channel sense amplifiers connected to said plurality of bit line pairs, respectively,  
 a plurality of power supply drive transistors provided corresponding to said plurality of P channel sense amplifiers, each power supply drive transistor being connected between said power supply line and a corresponding P channel sense amplifier,  
 a plurality of N channel sense amplifiers connected to said plurality of bit line pairs, respectively, and  
 a plurality of ground drive transistors provided corresponding to said plurality of N channel sense amplifiers, each ground drive transistor being connected between said ground line and a corresponding N channel sense amplifier.  
 
   
     
     
         16 . The semiconductor memory device according to  claim 15 , said plurality of memory cell arrays being arranged in a matrix, wherein 
 said power supply drive transistors in said memory cell array arranged in each row of said matrix are connected in common to said power supply line,    said ground drive transistors in said memory cell array arranged in each row of said matrix are connected in common to said ground line,    said power supply drive transistors in said memory cell array arranged in each column of said matrix are connected in common to said power supply line, and    said ground drive transistors in said memory cell array arranged in each column of said matrix are connected in common to said ground line.    
     
     
         17 . A semiconductor memory device comprising: 
 a word line driver connected to a select signal line corresponding to a word line to supply a voltage of said select signal line to said word line,    a row address detection circuit responsive to a row address signal to selectively activate said word line driver, and    a control circuit responsive to said row address signal to selectively supply a ground voltage or a negative voltage to said select signal line.    
     
     
         18 . A semiconductor memory device comprising: 
 a plurality of word line drivers, each connected to a plurality of word lines and a plurality of select signal lines corresponding to said plurality of word lines to supply voltages of said plurality of select signal lines to said plurality of word lines,    a row address detection circuit responsive to a row address signal to selectively activate said plurality of word line drivers, and    a control circuit responsive to said row address signal to selectively supply a ground voltage or a negative voltage to said plurality of select signal lines.    
     
     
         19 . The semiconductor memory device according to  claim 13 , wherein said control circuit comprises a plurality of control circuit units provided corresponding to said plurality of select signal lines, each said control circuit unit including 
 a first P channel MOS transistor having a gate connected to a first input node, a source connected to a power supply node and a drain connected to a corresponding select signal line,    a first N channel MOS transistor having a source connected to a negative voltage node, and a drain connected to said corresponding select signal line,    a first transmission transistor transmitting a voltage of said first input node to a gate of said first N channel MOS transistor,    a second N channel MOS transistor having a source connected to ground, and a drain connected to said corresponding select signal line,    a second P channel MOS transistor having a gate connected to a second input node, a source connected to a power supply node, and a drain connected to a gate of said second N channel MOS transistor,    a third N channel MOS transistor having a source connected to a negative voltage node and a drain connected to a gate of said second N channel MOS transistor, and    a second transmission transistor connected between said second input node and a gate of said third N channel MOS transistor, turned on constantly.    
     
     
         20 . The semiconductor memory device according to  claim 19 , further comprising: 
 a fourth N channel MOS transistor having a gate connected to said first input node, a drain connected to the drain of said first P channel MOS transistor, and a source connected to the drain of said first N channel MOS transistor, and    a fifth N channel MOS transistor having a gate connected to said second input node, a drain connected to the drain of said second P channel MOS transistor, and a source connected to the drain of said third N channel MOS transistor.