Test system

Abstract

The invention provides apparatus and a method of scan testing digital logic circuits, in particular faults in circuit operation during operational transitions in the circuit. The system is intended for use in testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; system disabling the external clock, synchronising testing means with the internal oscillating means, performing testing on the circuit while the external clock is disabled and re-enabling the external clock following testing. In the preferred embodiment, the test clock is synchronised with a PLL. The preferred embodiments address the difficulties with the conventional test methodology by synchronising the test clock with the phase locked loop internal to the IC. The advantages include: switching between external and PLL clocks is always clean, so that there are no “runt” pulses which would invalidate the test; there are no critical timings of external signals, so that it is possible to run very high speed scan-based transition fault tests (say 500 MHz) using low cost ATE capable only of modest speed (50 MHz) and pin edge placement accuracy; and the synchroniser circuit allows for a pre-programmed number of PLL pulses to be emitted to test faults which require several capture cycles to produce and capture the relevant transition.

What is claimed is:  
     
         1 . A method of scan testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; the method including the steps of disabling the external clock, synchronising testing means with the internal oscillating means, performing scan testing on the circuit while the external clock is disabled and re-enabling the external clock following testing.  
     
     
         2 . A method according to  claim 1 , wherein the oscillation means which is used is a phase locked loop within the logic circuit.  
     
     
         3 . A method according to  claim 1 , including the step of determining the length of time during which the external clock is disabled.  
     
     
         4 . A method according to  claim 1 , wherein for transition testing which includes a capture phase, the method includes the step of disabling propagation of the external clock prior to the capture phase, emitting a predetermined number of high speed oscillator pulses and switching back to the external clock to shift captured data off-chip.  
     
     
         5 . A method according to  claim 1 , including the step of enabling scan chain shifting, the method providing the external clock during such scan chain shifting.  
     
     
         6 . A system for scan testing a logic circuit which is driven by high frequency oscillating means and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; the system including a clock controller operable to disable the external clock, to synchronise testing means with the internal oscillating means, and to re-enable the external clock following testing on the circuit.  
     
     
         7 . A system according to  claim 6 , wherein the oscillation means is a phase locked loop.  
     
     
         8 . A system according to  claim 6 , wherein the controller includes means for setting the length of time during which the external clock is disabled.  
     
     
         9 . A system according to  claim 6 , wherein the controller is operable to provide the external clock signal for scan chain shifting testing.  
     
     
         10 . A method of scan testing a logic circuit which is driven by a high frequency phase locked loop (PLL) and an external clock, which external clock during normal operation is used to time control of the operation of the circuit, the method including the steps of: 
 a) during scan chain shifting using as the clock the external clock;    b) prior to capture cycles in a test capture phase disabling propagation of the external clock and switching to using the PLL;    c) during the test capture phase emitting a programmable number of high frequency PLL pulses;    d) at the end of the test capture switching back to the external clock.    
     
     
         11 . A system for scan testing a logic circuit which is driven by a high frequency phase locked loop (PLL) and an external clock, which external clock during normal operation is used to time control of the operation of the circuit; the system including: 
 a) means for providing the external clock during scan chain shifting;    b) means for disabling propagation of the external clock and switching to using the PLL prior to capture cycles in a test capture phase;    c) means for emitting a programmable number of high frequency PLL pulses during the test capture phase;    d) means for switching back to the external clock at the end of the test capture.