MOS-type semiconductor device and method for making same
Abstract
An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semiconductor property) different to the crystallographic orientation (or other respective property) of the other semiconductor. This arrangement of crystallographic orientations (and other crystallographic/semiconductor properties) can yield reduced unintended electron tunneling or current leakage through the insulator vis a vis a semiconductor device in which such an arrangement is not used. Methods for forming the MOS-type semiconductor devices of the invention are also provided.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An MOS-type semiconductor device comprising a first semiconductor, an insulator adjacent said first semiconductor, and a second semiconductor, wherein said first and second semiconductors are monocrystalline semiconductors having crystallographic axes and wherein the crystallographic axes of said first and second semiconductors are arranged in directions different to each other.
2 . The MOS-type semiconductor device of claim 1 , wherein said first and second semiconductors comprise silicon electrodes.
3 . The MOS-type semiconductor device of claim 1 wherein said insulator comprises an oxide thin layer.
4 . The MOS-type semiconductor of claim 2 , wherein said insulator comprises an oxide thin layer.
5 . The MOS-type semiconductor of claim 1 , wherein said insulator comprises an insulator formed by oxidation of a portion of said first semiconductor and wherein said second semiconductor has an atomically-flat surface bonded to said insulator.
6 . The MOS-type semiconductor of claim 1 , wherein said first semiconductor comprises an integrated circuit substrate and said second semiconductor comprises a gate electrode.
7 . The MOS-type semiconductor of claim 1 , wherein the [100] crystallographic orientation of said first semiconductor is orthogonal to a plane defined by the junction between said first semiconductor and said insulator and the [111] crystallographic orientation of said second semiconductor is orthogonal to the same plane.
8 . The MOS-type semiconductor of claim 7 , wherein said first and second semiconductors comprise silicon electrodes.
9 . The MOS-type semiconductor device of claim 8 , wherein said insulator comprises an oxide thin layer.
10 . The MOS-type semiconductor of claim 8 , wherein said insulator comprises an insulator formed by oxidation of a portion of said first semiconductor and wherein said second semiconductor has an atomically-flat surface bonded to said insulator.
11 . The MOS-type semiconductor of claim 8 , wherein said first semiconductor comprises an integrated circuit substrate and said second semiconductor comprises a gate electrode.
12 . The MOS-type semiconductor of claim 8 , wherein the conductivity of at least a portion of said first semiconductor and said second semiconductor are altered by an added dopant.
13 . The MOS-type semiconductor of claim 1 , wherein said second semiconductor comprises germanium.
14 . The MOS-type semiconductor of claim 1 , wherein said insulator comprises tantalum oxide.
15 . An MOS-type semiconductor device comprising a gate electrode for electrically coupling a transistor source and drain in an integrated circuit substrate in conjunction with an insulator, wherein said gate electrode has crystallographic properties distinct from respective crystallographic properties of said substrate, whereby electron tunneling through said insulator is reduced as compared to that which would occur if said gate electrode had crystallographic properties identical to the respective crystallographic properties of said substrate.
16 . The MOS-type semiconductor device of claim 15 , wherein said gate electrode has a [111] crystallographic direction that is orthogonal to the crystallographic orientation of an opposing surface of said substrate.
17 . The MOS-type semiconductor of claim 15 , wherein said gate electrode and said substrate both share a same crystallographic orientation but are formed of different chemical substances.
18 . A method for forming an MOS-type semiconductor device comprising the steps of:
(a) selecting first and second monocrystal semiconductor pieces (said pieces having crystallographic axes and wherein the crystallographic axes of said first and second pieces are arranged in directions different to each other) and providing each of said pieces with an atomically-flat surface; (b) providing an oxide layer on said atomically-flat surface of said second piece; (c) bonding said atomically-flat surface of said first piece to said oxide layer on said second piece; (d) performing processing upon said first piece to form it into an electrode; and (e) doping at least a portion of said first and second pieces.
19 . The method of claim 18 , wherein said first piece comprises monocrystal silicon of [111] crystallographic orientation and said second piece comprises monocrystal silicon of [100] orientation and wherein the step of performing processing upon said first piece to form it into an electrode comprises:
(1) grinding and polishing a surface of said first piece opposite said atomically-flat surface to reduce said first piece to a desired thickness; and (2) etching said first piece.
20 . The method of claim 18 wherein the step of providing an oxide layer on said atomically-flat surface of said second piece comprises conducting oxidation upon said atomically-flat surface of said second piece.
21 . A method for forming an MOS-type semiconductor device comprising the steps of:
(a) selecting a first monocrystal semiconductor piece (said piece having crystallographic axes and a substantially-flat surface); (b) providing an oxide layer on said substantially-flat surface of said first piece; (c) providing a layer comprising polycrystalline semiconductor material on said oxide layer, said polycrystalline semiconductor material layer comprising a plurality of bounded grains of monocrystal semiconductor material; (d) selecting at least one of said bounded grains of monocrystal semiconductor material; (e) performing processing upon said polycrystalline semiconductor material layer to:
(1) remove substantially all of said polycrystalline semiconductor material layer but for said selected bounded grain of monocrystal semiconductor material; and
(2) form said selected bounded grain of monocrystal semiconductor material into an electrode; and
(f) doping at least a portion of said first and second pieces.Join the waitlist — get patent alerts
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