High speed digital-to -analog converter

Abstract

An high speed analog-to-digital converter, for converting an analog input signal (u(t)) with a maximum frequency (F max ) to a digital output signal (x(n)) with an output sampling rate (F s ) at least double the maximum frequency (F max ), comprises a plurality of analog narrowband filters (F o -F M−1 ) for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X 0 -X M−1 ). Each narrowband filter has a passband. The sum of the gains of the narrowband filters at any frequency within an operating frequency band of the plurality of narrowband filters is substantially unity. Each of a corresponding plurality of analog-to-digital converter units (AD 0 -AD M−1 ) comprises a sample-and-hold device (SH) and a quantizer (Q). The sample-and-hold devices are clocked by a corresponding plurality of clock signals (Φ 0 -Φ M−1 ) respectively, each of the plurality of clock signals having a frequency at least double the bandwidth of the corresponding narrowband filter and an integer division of said predetermined sampling rate. The converter also comprises sampling and summing circuitry for sampling the outputs of the analog-to-digital converter units sequentially at the predetermined sampling rate (Fs) and summing the resulting sampled signals to produce the digital output signal (x(n)). The frequencies of the plurality of clock signals, and their phase-displacements relative to the output sampling clock signal, are such that each sample of the analog-to-digital converter output signal corresponds to a sampling edge of a different one of the sample-and-hold clock signal.

What is claimed is:  
     
         1 . An analog-to-digital converter for converting an analog input signal (u(t)) having a frequency up to a predetermined maximum frequency (F max ) to a digital output signal (x(n)) having a predetermined output sampling rate (F s ) equal to at least double the maximum frequency (F max ), the analog-to-digital converter comprising: 
 (i) a plurality of analog narrowband filters (F 0 -F M−1 ;F L ,F H ,F P ) for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X 0 -X M−1 ; X L ,X H ,X P ), 
 each narrowband filter having a passband, the sum of the gains of the narrowband filters at any frequency within an operating frequency band of the plurality of narrowband filters being substantially unity;  
   (ii) a corresponding plurality of sample-and-hold devices (SH 0 -SH M−1 ; SH L ,SH H ,SH P ) clocked by a plurality of clock signals (Φ 0 -Φ M−1 ), respectively, 
 each of the plurality of clock signals having a frequency at least double the bandwidth of the corresponding narrowband filter; and  
   (iii) a plurality of quantizers (Q 0 -Q M−1 ; Q L ,Q H ,Q P ) each connected to a respective one of the sample-and-hold devices (SH 0 -SH M−1 ; SH L ,SH H ,SH P ) and operable to provide a digitized value of each sample held by the corresponding sample-and-hold device;    (iv) sampling and summing means ( 12 ,R 0 -R M−1 ;  12   1 , 12   2 , 14 ;  12 , 14   1 , 14   2 ; R L ,R H ,R P ) for sampling and summing the outputs of the quantizers to produce said digital output signal (x(n)), the sampling being carried out sequentially at the predetermined sampling rate (Fs) in response to an output clock signal (CLK), the frequencies and phase-relationships of the plurality of clock signals (Φ 0 -Φ M−1 ) being such that each sample point of the output clock signal coincides with a sample point of one of the plurality of clock signals.    
     
     
         2 . An analog-to-digital converter according to  claim 1 , wherein the sampling-and-summing means ( 12 ,  12   1 ,  12   2    14 ,  14   1 ,  14   2 , R 0 -R M−1 ,) comprises means (R L -R H ) for sampling the outputs of the quantizers at the predetermined rate (F s ) and means ( 12 ′) for summing the samples from the sampling means (R 0 -R M−1 ).  
     
     
         3 . An analog-to-digital converter according to  claim 1 , wherein the sampling-and-summing means ( 12 ,  12   1 ,  12   2    14 ,  14   1 ,  14   2 , R 0 -R M−1 ,) comprises summing means ( 12   1 - 12   2 ) for summing digitized values from the plurality of quantizers and sampling means ( 14 ) for sampling the summed digitized values.  
     
     
         4 . An analog-to-digital converter according to  claim 1 , wherein the plurality of narrowband filters all have the same bandwidth equal to one half of said predetermined output sampling rate (Fs) divided by the number (M) of said narrowband signals (X 0 -X M−1 ), and said plurality of clock signals (Φ 0 -Φ M−1 ) all have the same frequency and are uniformly phase-displaced relative to each other by a phase angle equal to one cycle of said same frequency divided by the number (M) of said plurality of clock signals.  
     
     
         5 . An analog-to-digital converter according to  claim 1 , wherein the plurality of analog narrowband filters have non-uniform bandwidths for filtering the analog input signal (u(t)) to produce a corresponding plurality of narrowband signals (X 0 -X M−1 ) having different bandwidths.  
     
     
         6 . A digital-to-analog converter, for converting a digital input signal (x(n)) into an analog output signal (u(t)), comprising an analog synthesis filter bank (DA 0 -DA M−1 ) having a plurality of inputs and a plurality of outputs, the plurality of outputs being connected in common to a summing device ( 2 ) for summing respective output signals from the synthesis filter bank to provide an analog output signal (u(t)), and a plurality of digital-to-analog converter units (DA 0 -DA M−1 ) having their inputs connected in common to receive the digital input signal (x(n)) and each having its output connected to a respective one of said plurality of inputs of the synthesis filter bank (DA 0 -DA M−1 ), the digital-to-analog converter units (DA 0 -DA M−1 ) being clocked by a plurality of clock signals (Φ 0 -Φ M−1 ), respectively, the frequencies and relative phase differences of the plurality of clock signals ((Φ 0 -Φ M−1 ) being arranged so that a sampling point of the input digital signal (x(n)) coincides with a sampling point of one of the plurality of clock signals (Φ 0 -Φ M−1 ).