Low power SRAM memory cell having a single bit line

Abstract

A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided. According to the method, the level of the bit line is set in accordance with data to be written, the memory cell is precharged so as to force the output of one of the inverters of the memory cell to a predetermined logic level, and the word line is activated to couple the bit line to the memory cell.

What is claimed is:  
     
         1 . A semiconductor memory cell comprising: 
 a word line;    a bit line;    a precharge line;    first and second cross-coupled inverters, the first inverter including a first P-channel transistor and a first N-channel transistor, and the second inverter including a second P-channel transistor and a second N-channel transistor;    an access transistor that selectively couples the bit line to an output of the first inverter; and    a precharge transistor connected between a predetermined voltage and the output of one of the first inverter and the second inverter,    wherein the gate terminal of the precharge transistor is connected to the precharge line.    
     
     
         2 . The semiconductor memory cell as defined in  claim 1 , wherein the predetermined voltage is ground.  
     
     
         3 . The semiconductor memory cell as defined in  claim 1 , wherein the source terminal of the first N-channel transistor of the first inverter and the source terminal of the second N-channel transistor of the second inverter are connected to ground.  
     
     
         4 . The semiconductor memory cell as defined in  claim 1 , wherein the precharge transistor is connected between a predetermined voltage and the output of the second inverter.  
     
     
         5 . The semiconductor memory cell as defined in  claim 4 , wherein the predetermined voltage is ground.  
     
     
         6 . The semiconductor memory cell as defined in  claim 5 , wherein the source terminal of the first N-channel transistor of the first inverter and the source terminal of the second N-channel transistor of the second inverter are connected to ground.  
     
     
         7 . The semiconductor memory cell as defined in  claim 1 , wherein the gate terminal of the access transistor is connected to the word line.  
     
     
         8 . The semiconductor memory cell as defined in  claim 1 , further comprising a control circuit that supplies a pulse signal to the precharge line during a writing operation for the memory cell.  
     
     
         9 . The semiconductor memory cell as defined in  claim 1 , further comprising a control circuit that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line.  
     
     
         10 . The semiconductor memory cell as defined in  claim 1 , wherein the memory cell is a static RAM memory cell.  
     
     
         11 . A semiconductor memory device comprising: 
 a plurality of word lines;    a plurality of bit lines;    a plurality of precharge lines; and    a plurality of memory cells coupled to the word lines, bit lines, and precharge lines, each of the memory cells including: 
 first and second cross-coupled inverters, the first inverter including a first P-channel transistor and a first N-channel transistor, and the second inverter including a second P-channel transistor and a second N-channel transistor;  
 an access transistor that selectively couples an output of one of the first inverter and the second inverter to one of the bit lines; and  
 a precharge transistor connected between a predetermined voltage and the output of the first inverter, the gate terminal of the precharge transistor being connected to the precharge line.  
   
     
     
         12 . The semiconductor memory device as defined in  claim 11 , wherein the predetermined voltage is ground.  
     
     
         13 . The semiconductor memory device as defined in  claim 11 , wherein for each of the memory cells, the source terminal of the first N-channel transistor of the first inverter and the source terminal of the second N-channel transistor of the second inverter are connected to ground.  
     
     
         14 . The semiconductor memory device as defined in  claim 11 , wherein for each of the memory cells, the access transistor selectively couples the output of the second inverter to one of the bit lines.  
     
     
         15 . The semiconductor memory device as defined in  claim 11 , further comprising a control circuit that supplies a pulse signal to at least one of the precharge lines during a writing operation for the memory device.  
     
     
         16 . The semiconductor memory device as defined in  claim 11 , further comprising a control circuit that, during a writing operation, supplies data to be written to one of the memory cells to one of the bit lines, supplies a pulse signal to at least one of the precharge lines, and activates at least one of the word lines.  
     
     
         17 . The semiconductor memory device as defined in  claim 11 , wherein the precharge lines run parallel to the word lines.  
     
     
         18 . The semiconductor memory device as defined in  claim 11 , wherein each of the precharge lines is commonly coupled to all of the memory cells that are coupled to one of the word lines.